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? 2005 microchip technology inc. preliminary ds70135c DSPIC30F4011/4012 data sheet high performance digital signal controllers
ds70135c-page ii preliminary ? 2005 microchip technology inc. information contained in this publication regarding device applications and the like is in tended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rf pic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratab le memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mpasm, mplib, mplink, mpsim, pickit, picdem, picd em.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s. a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2005, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. 11/12/04 note the following details of the code protection fe ature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of produc ts is one of the most secure families of its kind on the market today, when used i n the intended manner and und er normal conditions. there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work wi th the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and moun tain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolat ile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development sys tems is iso 9001:2000 certified.
? 2005 microchip technology inc. preliminary ds70135c-page 1 DSPIC30F4011/4012 high performance modified risc cpu: modified harvard architecture c compiler optimized inst ruction set architecture with flexible addressing modes 84 base instructions 24-bit wide instructions, 16-bit wide data path 48 kbytes on-chip flash program space (16k instruction words) 2 kbytes of on-chip data ram 1 kbytes of non-volatile data eeprom up to 30 mips operation: - dc to 40 mhz external clock input - 4 mhz-10 mhz oscillator input with pll active (4x, 8x, 16x) 30 interrupt sources - 3 external interrupt sources - 8 user selectable priority levels for each interrupt source - 4 processor trap sources 16 x 16-bit working register array dsp engine features: dual data fetch accumulator write back for dsp operations modulo and bit-reve rsed addressing modes two, 40-bit wide accumu lators with optional saturation logic 17-bit x 17-bit single cycle hardware fractional/ integer multiplier all dsp instructions single cycle 16-bit single cycle shift peripheral features: high current sink/source i/o pins: 25 ma/25 ma timer module with programmable prescaler: - five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules 16-bit capture input functions 16-bit compare/pwm output functions 3-wire spi? modules (s upports 4 frame modes) i 2 c? module supports multi-master/slave mode and 7-bit/10-bit addressing 2 uart modules with fifo buffers 1 can modules, 2.0b compliant motor control pwm module features: 6 pwm output channels - complementary or independent output modes - edge and center aligned modes 3 duty cycle generators dedicated time base programmable output polarity dead-time control for complementary mode manual output control trigger for a/d conversions quadrature encoder interface module features: phase a, phase b and index pulse input 16-bit up/down position counter count direction status position measurement (x2 and x4) mode programmable digital noise filters on inputs alternate 16-bit timer/counter mode interrupt on position count er rollover/underflow note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). DSPIC30F4011/4012 enhanced flash 16-bit digital signal controller
DSPIC30F4011/4012 ds70135c-page 2 preliminary ? 2005 microchip technology inc. analog features: 10-bit analog-to-digita l converter (a/d) with 4 s/h inputs: - 500 ksps conversion rate - 9 input channels - conversion available during sleep and idle programmable brown-ou t detection and reset generation special microcontroller features: enhanced flash program memory: - 10,000 erase/write cycle (min.) for industrial temperatur e range, 100k (typical) data eeprom memory: - 100,000 erase/write cycle (min.) for industrial temperatur e range, 1m (typical) self-reprogrammable under software control power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) flexible watchdog timer (wdt) with on-chip low power rc oscillator fo r reliable operation fail-safe clock monitor operation detects clock failure and switches to on-chip low power rc oscillator programmable code protection in-circuit serial programming? (icsp?) selectable power management modes - sleep, idle and al ternate clock modes cmos technology: low power, high speed flash technology wide operating voltage range (2.5v to 5.5v) industrial and extend ed temperature ranges low power consumption dspic30f motor control and power conversion family* device pins program mem. bytes/ instructions sram bytes eeprom bytes timer 16-bit input cap output comp/std pwm moto control pwm a/d 10-bit 500 ksps quad enc uart spi ? i 2 c ? can dspic30f2010 28 12k/4k 512 1024 3 4 2 6 ch 6 ch yes 1 1 1 - dspic30f3010 28 24k/8k 1024 1024 5 4 2 6 ch 6 ch yes 1 1 1 - dspic30f4012 28 48k/16k 2048 1024 5 4 2 6 ch 6 ch yes 1 1 1 1 dspic30f3011 40/44 24k/8k 1024 1024 5 4 4 6 ch 9 ch yes 2 1 1 - DSPIC30F4011 40/44 48k/16k 2048 1024 5 4 4 6 ch 9 ch yes 2 1 1 1 dspic30f5015 64 66k/22k 2048 1024 5 4 4 8 ch 16 ch yes 1 2 1 1 dspic30f6010 80 144k/48k 8192 4096 5 8 8 8 ch 16 ch yes 2 2 1 2 * this table provides a summary of the dspic30f6010 periph eral features. other available devices in the dspic30f motor control and power co nversion family are shown for feature comparison.
? 2005 microchip technology inc. preliminary ds70135c-page 3 DSPIC30F4011/4012 pin diagrams an7/rb7 an6/ocfa/rb6 c1rx/rf0 c1tx/rf1 oc3/rd2 emuc2/oc1/ic1/int1/rd0 an8/rb8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DSPIC30F4011 mclr v dd v ss emud2/oc2/ic2/int2/rd1 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 osc2/clko/rc15 osc1/clkin pwm1l/re0 pwm1h/re1 pwm2l/re2 pwm2h/re3 pwm3h/re5 av dd av ss oc4/rd3 v ss v dd sck1/rf6 pgc/emuc/u1rx/sdi1/sda/rf2 pgd/emud/u1tx/sdo1/scl/rf3 pwm3l/re4 v dd u2rx/cn17/rf4 u2tx/cn18/rf5 an4/qea/ic7/cn6/rb4 an2/ss1/cn4/rb2 emuc3/an1/v ref -/cn3/rb1 emud3/an0/v ref +/cn2/rb0 an5/qeb/ic8/cn7/rb5 flta/int0/re8 v ss an3/indx/cn5/rb3 40-pin pdip 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 pgd/emud/u1tx/sdo1/scl/rf3 sck1/rf6 emuc2/oc1/ic1/int1/rd0 oc3/rd2 v dd emuc1/sosco/t1ck/u1arx/cn0/rc14 nc v ss oc4/rd3 emud2/oc2/ic2/int2/rd1 flta/int0/re8 an3/indx/cn5/rb3 an2/ss1/cn4/rb2 emuc3/an1/v ref -/cn3/rb1 emud3/an0/v ref +/cn2/rb0 mclr nc av dd av ss pwm1l/re0 pwm1h/re1 pwm2h/re3 pwm3l/re4 pwm3h/re5 v dd v ss crx1/rf0 ctx1/rf1 u2rx/cn17/rf4 u2tx/cn18/rf5 pgc/emuc/u1rx/sdi1/sda/rf2 an4/qea/ic7/cn6/rb4 an5/qeb/ic8/cn7/rb5 an6/ocfa/rb6 an7/rb7 an8/rb8 nc v dd v ss osc1/clkin osc2/clko/rc15 emud1/sosci/t2ck/u1atx/cn1/rc13 44-pin tqfp DSPIC30F4011 pwm2l/re2 nc
DSPIC30F4011/4012 ds70135c-page 4 preliminary ? 2005 microchip technology inc. pin diagrams (continued) 44-pin qfn 44 43 42 41 40 39 38 37 36 35 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 DSPIC30F4011 pwm2h/re3 pwm3l/re4 pwm3h/re5 v dd v dd crx1/rf0 ctx1/rf1 u2rx/cn17/rf4 u2tx/cn18/rf5 pgc/emuc/u1rx/sdi1/sda/rf2 an3/indx/cn5/rb3 an2/ss1/cn4/rb2 emuc3/an1/v ref -/cn3/rb1 emud3/an0/v ref +/cn2/rb0 mclr av dd pwm1l/re0 pwm1h/re1 pwm2l/re2 an4/qea/ic7/cn6/rb4 an5/qeb/ic8/cn7/rb5 an6/ocfa/rb6 an7/rb7 an8/rb8 v dd v ss osc1/clkin osc2/clko/rc15 pgd/emud/u1tx/sdo1/scl/rf3 sck1/rf6 emuc2/oc1/ic1/int1/rd0 oc3/rd2 v dd emuc1/sosco/t1ck/u1arx/cn0/rc14 oc4/rd3 emud2/oc2/ic2/int2/rd1 flta/int0/re8 6 22 33 34 v ss av ss v dd v ss emud1/sosci/t2ck/u1atx/cn1/rc13 v ss nc 12 13
? 2005 microchip technology inc. preliminary ds70135c-page 5 DSPIC30F4011/4012 pin diagrams (continued) dspic30f4012 mclr pwm1l/re0 pwm1h/re1 pwm2l/re2 pwm2h/re3 pwm3l/re4 pwm3h/re5 v ss v dd emud3/an0/v ref +/cn2/rb0 emuc3/an1/v ref -/cn3/rb1 av dd av ss an2/ss1/cn4/rb2 emud2/oc2/ic2/int2/rd1 emuc2/oc1/ic1/int1/rd0 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 v ss osc2/clko/rc15 osc1/clkin v dd flta/int0/sck1/ocfa/re8 pgc/emuc/u1rx/sdi1/sda/c1rx/rf2 pgd/emud/u1tx/sdo1/scl/c1tx/rf3 an5/qeb/ic8/cn7/rb5 an4/qea/ic7/cn6/rb4 an3/indx/cn5/rb3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin spdip 28-pin soic 44-pin qfn 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 dspic30f4012 pwm2h/re3 pwm3l/re4 pwm3h/re5 v dd v dd nc nc nc nc pgc/emuc/u1rx/sdi1/sda/c1rx/rf2 an3/indx/cn5/rb3 an2/ss1/cn4/rb2 emuc3/an1/v ref -/cn3/rb1 emud3/an0/v ref +/cn2/rb0 mclr av dd pwm1l/re0 pwm1h/re1 pwm2l/re2 an4/qea/ic7/cn6/rb4 an5/qeb/ic8/cn7/rb5 nc nc nc v dd v ss osc1/clkin osc2/clko/rc15 pgd/emud/u1tx/sdo1/scl/c1tx/rf3 flta/int0/sck1/ocfa/re8 emuc2/oc1/ic1/int1/rd0 nc v dd emuc1/sosco/t1ck/u1arx/cn0/rc14 nc emud2/oc2/ic2/int2/rd1 v dd 6 33 v ss av ss v dd v ss emud1/sosci/t2ck/u1atx/cn1/rc13 v ss nc 14 15 16 17 18 19 20 21 22 12 13 44 43 42 41 40 39 38 37 36 35 34
DSPIC30F4011/4012 ds70135c-page 6 preliminary ? 2005 microchip technology inc. table of contents 1.0 device overview ............. .................... ..................... .................... .................. ................. ................... .................... .................. 7 2.0 cpu architecture overview........... ...................... ....................... ...................... ..................... ................. .................. .............. 15 3.0 memory organization ........... .................... .................... .................. .................. .................. .................. .................. ................ 23 4.0 address generator units................. ...................... ....................... .................... ................... ................. .................. ................ 35 5.0 interrupts .................. ..................... .................... .................... .................. ................. .............................. .................. .............. 41 6.0 flash program memory................. ...................... ....................... ...................... .................... .................. .................. .............. 47 7.0 data eeprom memory ........... .................... ..................... .................. .................. .................. .................. ............... .............. 53 8.0 i/o ports ............. ...................... .................... ..................... .................... ................... .............................. .................. .............. 57 9.0 timer1 module ................ .................... ..................... .................. .................. .................. ............................. ................ ........... 63 10.0 timer2/3 module ............. .................... ..................... .................. .................. .................. .................... .................... ................ 67 11.0 timer4/5 module ............ .................... ..................... .................. .................. .................. .................... .................... ................ 73 12.0 input capture module................. ....................... ...................... ..................... .................... .................... .................. ................ 77 13.0 output compare module ................. ...................... ....................... .................... .................... .................. .................. .............. 81 14.0 quadrature encoder interface (qei) modul e .......................... ..................... .................. ................. ..................... .................. 85 15.0 motor control pwm module ... .................... .................... ..................... .................. ................. ......................... .............. ......... 91 16.0 spi? module .................. .................... ..................... .................. .................. ................. ............................ ............... ............ 101 17.0 i2c? module .................. .................... ..................... .................. .................. ................. ............................ ............... ............ 105 18.0 universal asynchronous receiver trans mitter (uart) module . ..................... ....................... ..................... ............ ............ 113 19.0 can module .................. .................... .................... ..................... .................. ................ .................... .................... ................ 121 20.0 10-bit high speed analog-to-digital converter (a/d) module .... ...................... .................... ................... ............... .............. 131 21.0 system integration .......... .................... ..................... .................. .................. .................. .................... .................. ................ 139 22.0 instruction set summary ............... ...................... ....................... .................... .................... .................. .................. .............. 153 23.0 development support.................... ...................... ....................... .................... ................... ................. .................. ................ 161 24.0 electrical characteristics ............ ....................... ...................... ..................... ................... ................... .................. ................ 167 25.0 packaging information................ ....................... ...................... ..................... .................... .................. .................. ................ 209 the microchip web site ......... ..................... .................... .................... .................. ................. .............................. ................ .............. 223 customer change notification service ....... ...................... ....................... .................... ................... ................. .................. ................ 223 customer support .............. .................... .................... ..................... .................. .................. ..................... ..................... ..................... 223 reader response ............ .................... .................... .................... ..................... ................... .............................. .................. .............. 224 product identification system.... .................... .................... .................. .................. .................. ....................... .................. .................. 225 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its li terature number found on the bo ttom outside corner of any page . the last character of the literature number is the versio n number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sale s office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2005 microchip technology inc. preliminary ds70135c-page 7 DSPIC30F4011/4012 1.0 device overview this document contains device specific information for the DSPIC30F4011/4012 device. the dspic30f devices contain extensive digital signal processor (dsp) functionality within a high performance 16-bit microcontroller (mcu) architecture. figure 1-1 and figure 1-2 show device block diagrams for the DSPIC30F4011 and dspic30f4012 device. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030).
DSPIC30F4011/4012 ds70135c-page 8 preliminary ? 2005 microchip technology inc. figure 1-1: DSPIC30F4011 block diagram an8/rb8 power-up timer oscillator start-up timer por/bor reset watchdog timer instruction decode and control osc1/clki mclr v dd , v ss an4/qea/cn6/ic7/rb4 uart1, spi1 motor control pwm timing generation can an5/qeb/cn7/ic8/rb5 16 pch pcl program counter alu<16> 16 address latch program memory (48 kbytes) data latch 24 24 24 24 x data bus ir i 2 c qei an6/ocfa/rb6 an7/rb7 pcu pwm1l/re0 pwm1h/re1 pwm2l/re2 pwm2h/re3 pwm3l/re4 10-bit adc timers pwm3h/re5 flta/int0/re8 u2tx/cn18/rf5 sck1/rf6 input capture module output compare module emuc1/sosco/t1ck /cn0/u1arx/rc14 emud1/sosci/cn1/t2ck/u1atx/rc13 portb c1rx/rf0 c1tx/rf1 u1rx/pgc/emuc/sdi1/sda/rf2 u1tx/pgd/emud/sdo1/scl/rf3 portf portd 16 16 16 16 x 16 w reg array divide unit engine dsp decode rom latch 16 y data bus effective address x ragu x wagu y agu an0/emud3/v ref +/cn2/rb0 an1/emuc3/v ref -/cn3/rb1 an2/ss1 /cn4/rb2 an3/indx/cn5/rb3 osc2/clko/rc15 u2rx/cn17/rf4 av dd , av ss uart2 16 16 16 16 16 portc porte 16 16 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic data latch data latch y data (1 kbyte) ram x data (1 kbyte) ram address latch address latch control signals to various blocks emuc2/oc1/ic1/int1/rd0 emud2/oc2/ic2/int2/rd1 oc3/rd2 oc4/rd3 16 data eeprom (1 kbyte) 16
? 2005 microchip technology inc. preliminary ds70135c-page 9 DSPIC30F4011/4012 figure 1-2: dspic30f4012 block diagram power-up timer oscillator start-up timer por/bor reset watchdog timer instruction decode and control osc1/clki mclr v dd , v ss an4/qea/cn6/ic7/rb4 uart1, spi1, motor control pwm timing generation can an5/qeb/cn7/ic8/rb5 16 pch pcl program counter alu<16> 16 address latch program memory (48 kbytes) data latch 24 24 24 24 x data bus ir i 2 c qei pcu pwm1l/re0 pwm1h/re1 pwm2l/re2 pwm2h/re3 pwm3l/re4 10-bit adc timers pwm3h/re5 flta/int0/sck1/ocfa/re8 input capture module output compare module emuc1/sosco/t1ck/cn0/u1arx/rc14 emud1/sosci/cn1/t2ck/u1atx/rc13 portb u1rx/pgc/emuc/sdi1/sda/rf2 u1tx/pgd/emud/sdo1/scl/rf3 portf portd 16 16 16 16 x 16 w reg array divide unit engine dsp decode rom latch 16 y data bus effective address x ragu x wagu y agu an0/cn2/v ref +/emud2/rb0 an1/cn3/v ref -/emuc3/rb1 an2/ss1 /cn4/rb2 an3/indx/cn5/rb3 osc2/clko/rc15 av dd , av ss uart2 16 16 16 16 16 portc porte 16 16 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic data latch data latch y data (1 kbyte) ram x data (1 kbyte) ram address latch address latch control signals to various blocks emuc2/oc1/rd0 emud2/oc2/rd1 16 data eeprom (1 kbyte) 16 spi2
DSPIC30F4011/4012 ds70135c-page 10 preliminary ? 2005 microchip technology inc. table 1-1 provides a brief description of the device i/o pinout and the functions that are multiplexed to a port pin. multiple functions may exist on one port pin. when multiplexing occurs, the peri pheral module?s functional requirements may force an override of the data direction of the port pin. table 1-1: DSPIC30F4011 i/o pin descriptions pin name pin type buffer type description an0-an8 i analog analog input channels. an0 and an1 are also used for device programming data and clock inputs, respectively. av dd p p positive supply for analog module. av ss p p ground reference for analog module. clki clko i o st/cmos ? external clock source input. always associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally function s as clko in rc and ec modes. always associated with osc2 pin function. cn0-cn7 cn17-cn18 i st input change notification inputs. can be software programmed for intern al weak pull-ups on all inputs. c1rx c1tx i o st ? can1 bus receive pin. can1 bus transmit pin. emud emuc emud1 emuc1 emud2 emuc2 emud3 emuc3 i/o i/o i/o i/o i/o i/o i/o i/o st st st st st st st st icd primary communication channel data input/output pin. icd primary communication ch annel clock input/output pin. icd secondary communication ch annel data input/output pin. icd secondary communication ch annel clock input/output pin. icd tertiary communication ch annel data input/output pin. icd tertiary communication ch annel clock input/output pin. icd quaternary communication channel data input/output pin. icd quaternary communication channel clock i nput/output pin. ic1, ic2, ic7, ic8 i st capture inputs 1, 2, 7 and 8. indx qea qeb i i i st st st quadrature encoder index pulse input. quadrature encoder phas e a input in qei mode. auxiliary timer external cloc k/gate input in timer mode. quadrature encoder phas e a input in qei mode. auxiliary timer external cloc k/gate input in timer mode. int0 int1 int2 i i i st st st external interrupt 0. external interrupt 1. external interrupt 2. flta pwm1l pwm1h pwm2l pwm2h pwm3l pwm3h i o o o o o o st ? ? ? ? ? ? pwm fault a input. pwm 1 low output. pwm 1 high output. pwm 2 low output. pwm 2 high output. pwm 3 low output. pwm 3 high output. mclr i/p st master clear (reset) input or progra mming voltage input. this pin is an active low reset to the device. ocfa oc1-oc4 i o st ? compare fault a input (for comp are channels 1, 2, 3 and 4). compare outputs 1 through 4. legend: cmos = cmos compatible input or output analog = analog input st = schmitt trigger input with cmos levels o = output i = input p = power
? 2005 microchip technology inc. preliminary ds70135c-page 11 DSPIC30F4011/4012 osc1 osc2 i i/o st/cmos ? oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. co nnects to crystal or resonat or in crystal oscillator mode. optionally functions as clko in rc and ec modes. pgd pgc i/o i st st in-circuit serial programming data input/output pin. in-circuit serial prog ramming clock input pin. rb0-rb8 i/o st portb is a bidirectional i/o port. 8rc13-rc15 8i/o 8st portc is a bidirectional i/o port. rd0-rd3 i/o st portd is a bidirectional i/o port. re0-re5, re8 i/o st porte is a bidirectional i/o port. rf0-rf6 i/o st portf is a bidirectional i/o port. sck1 sdi1 sdo1 ss1 i/o i o i st st ? st synchronous serial clock input/output for spi? 1. spi 1 data in. spi 1 data out. spi 1 slave synchronization. scl sda i/o i/o st st synchronous serial clock input/output for i 2 c. synchronous serial data input/output for i 2 c. sosco sosci o i ? st/cmos 32 khz low power oscillator crystal output. 32 khz low power oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. t1ck t2ck i i st st timer1 external clock input. timer2 external clock input. u1rx u1tx u1arx u1atx u2rx u2tx i o i o i o st ? st ? st ? uart1 receive. uart1 transmit. uart1 alternate receive. uart1 alternate transmit. uart2 receive. uart2 transmit. v dd p ? positive supply for logic and i/o pins. v ss p ? ground reference for logic and i/o pins. v ref + i analog analog voltage reference (high) input. v ref - i analog analog voltage reference (low) input. table 1-1: DSPIC30F4011 i/o pin descriptions (continued) pin name pin type buffer type description legend: cmos = cmos compatible inpu t or output analog = analog input st = schmitt trigger input with cmos levels o = output i = input p = power
DSPIC30F4011/4012 ds70135c-page 12 preliminary ? 2005 microchip technology inc. table 1-2 provides a brief description of the device i/o pinout and the functions that are multiplexed to a port pin. multiple functions may exist on one port pin. when multiplexing occurs, the peri pheral module?s functional requirements may force an override of the data direction of the port pin. table 1-2: dspic30f4012 i/o pin descriptions pin name pin type buffer type description an0-an5 i analog analog input channels. an0 and an1 are also used for device programming data and clock inputs, respectively. av dd p p positive supply for analog module. av ss p p ground reference for analog module. clki clko i o st/cmos ? external clock source input. always associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally function s as clko in rc and ec modes. always associated with osc2 pin function. cn0-cn7 i st input change notification inputs. can be software programmed for intern al weak pull-ups on all inputs. c1rx c1tx i o st ? can1 bus receive pin. can1 bus transmit pin. emud emuc emud1 emuc1 emud2 emuc2 emud3 emuc3 i/o i/o i/o i/o i/o i/o i/o i/o st st st st st st st st icd primary communication channel data input/output pin. icd primary communication ch annel clock input/output pin. icd secondary communication ch annel data input/output pin. icd secondary communication ch annel clock input/output pin. icd tertiary communication ch annel data input/output pin. icd tertiary communication ch annel clock input/output pin. icd quaternary communication channel data input/output pin. icd quaternary communication channel clock i nput/output pin. ic1, ic2, ic7, ic8 i st capture inputs 1, 2, 7 and 8. indx qea qeb i i i st st st quadrature encoder index pulse input. quadrature encoder phas e a input in qei mode. auxiliary timer external cloc k/gate input in timer mode. quadrature encoder phas e a input in qei mode. auxiliary timer external cloc k/gate input in timer mode. int0 int1 int2 i i i st st st external interrupt 0. external interrupt 1. external interrupt 2. flta pwm1l pwm1h pwm2l pwm2h pwm3l pwm3h i o o o o o o st ? ? ? ? ? ? pwm fault a input. pwm 1 low output. pwm 1 high output. pwm 2 low output. pwm 2 high output. pwm 3 low output. pwm 3 high output. mclr i/p st master clear (reset) input or progra mming voltage input. this pin is an active low reset to the device. ocfa oc1, oc2 i o st ? compare fault a input (for comp are channels 1, 2, 3 and 4). compare outputs 1 and 2. legend: cmos = cmos compatible input or output analog = analog input st = schmitt trigger input with cmos levels o = output i = input p = power
? 2005 microchip technology inc. preliminary ds70135c-page 13 DSPIC30F4011/4012 osc1 osc2 i i/o st/cmos ? oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. co nnects to crystal or resonat or in crystal oscillator mode. optionally functions as clko in rc and ec modes. pgd pgc i/o i st st in-circuit serial programming data input/output pin. in-circuit serial prog ramming clock input pin. rb0-rb5 i/o st portb is a bidirectional i/o port. rc13-rc15 8i/o 8st portc is a bidirectional i/o port. rd0-rd1 i/o st portd is a bidirectional i/o port. re0-re5, re8 i/o st porte is a bidirectional i/o port. rf2-rf3 i/o st portf is a bidirectional i/o port. sck1 sdi1 sdo1 i/o i o st st ? synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. scl sda i/o i/o st st synchronous serial clock input/output for i 2 c. synchronous serial data input/output for i 2 c. sosco sosci o i ? st/cmos 32 khz low power oscillator crystal output. 32 khz low power oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. t1ck t2ck i i st st timer1 external clock input. timer2 external clock input. u1rx u1tx u1arx u1atx i o i o st ? st ? uart1 receive. uart1 transmit. uart1 alternate receive. uart1 alternate transmit. v dd p ? positive supply for logic and i/o pins. v ss p ? ground reference for logic and i/o pins. v ref + i analog analog voltage reference (high) input. v ref - i analog analog voltage reference (low) input. table 1-2: dspic30f4012 i/o pin descriptions (continued) pin name pin type buffer type description legend: cmos = cmos compatible inpu t or output analog = analog input st = schmitt trigger input with cmos levels o = output i = input p = power
DSPIC30F4011/4012 ds70135c-page 14 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 15 DSPIC30F4011/4012 2.0 cpu architecture overview this document provides a summary of the DSPIC30F4011/4012 cpu and peripheral function. for a complete description of this functionality, please refer to the dspic30f family reference manual (ds70046). 2.1 core overview the core has a 24-bit instruction word. the program counter (pc) is 23 bits wide with the least significant (ls) bit always clear (see section 3.1), and the most significant (ms) bit is ignored during normal program execution, except for certain specialized instructions. thus, the pc can address up to 4m instruction words of user program space. an instruction pre-fetch mech- anism is used to help maintain throughput. program loop constructs, free from loop count management overhead, are supported using the do and repeat instructions, both of which are interruptible at any point. the working register array consists of 16x16-bit regis- ters, each of which can act as data, address or offset registers. one working register (w15) operates as a software stack pointer fo r interrupts and calls. the data space is 64 kbytes (32k words) and is split into two blocks, referred to as x and y data memory. each block has its own in dependent address genera- tion unit (agu). most in structions operate solely through the x memory agu, which provides the appearance of a single unified data space. the multiply-accumulate ( mac ) class of dual source dsp instructions operate thro ugh both the x and y agus, splitting the data address space into two parts (see section 3.2). the x and y data space boundary is device specific and cannot be altered by the user. each data word consists of 2 bytes, and most instructions can address data either as words or bytes. there are two methods of accessing data stored in program memory: the upper 32 kbytes of data space memory can be mapped into the lower ha lf (user space) of pro- gram space at any 16k program word boundary, defined by the 8-bit program space visibility page (psvpag) register. this lets any instruction access program space as if it were data space, with a limitation that the access requires an addi- tional cycle. moreover, only the lower 16 bits of each instruction word ca n be accessed using this method. swwlinear indirect acce ss of 32k word pages within program space is also possible using any working register, via tabl e read and write instruc- tions. table read and wr ite instructions can be used to access all 24 bits of an instruction word. overhead-free circular buff ers (modulo addressing) are supported in both x and y a ddress spaces. this is pri- marily intended to remove the loop overhead for dsp algorithms. the x agu also supports bit-reversed addressing on destination effective addresses , to greatly simplify input or output data reordering for radix-2 fft algorithms. refer to section 4.0 for details on modulo and bit-reversed addressing. the core supports inherent (no operand), relative, lit- eral, memory direct, register direct, register indirect, register offset and litera l offset addressing modes. instructions are associated with predefined addressing modes, depending upon thei r functional requirements. for most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, 3-operand instructi ons are supported, allowing c = a+b operations to be ex ecuted in a single cycle. a dsp engine has been in cluded to significantly enhance the core arithmetic capability and throughput. it features a high speed 17- bit by 17-bit multiplier, a 40-bit alu, two 40-bit saturating accumulators and a 40-bit bi-directional barrel shifter. data in the accumu- lator or any working register can be shifted up to 16 bits right or 16 bits left in a single cycle. the dsp instruc- tions operate seamlessly with all other instructions and have been designed for opti mal real-time performance. the mac class of instructions can concurrently fetch two data operands from memory, while multiplying two w registers. to enable this concurrent fetching of data operands, the data space has been split for these instructions and linear fo r all others. this has been achieved in a transparent and flexible manner, by dedicating certain working r egisters to each address space for the mac class of instructions. the core does not support a multi-stage instruction pipeline. however, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. most instructions execute in a single cycle, with certain exceptions. the core features a vectored exception processing structure for traps and inte rrupts, with 62 independent vectors. the exceptions cons ist of up to 8 traps (of which 4 are reserved) and 54 interrupts. each interrupt is prioritized based on a us er assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest) in conjunction with a predetermined ?natural order?. traps have fixed priori ties, ranging from 8 to 15. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030).
DSPIC30F4011/4012 ds70135c-page 16 preliminary ? 2005 microchip technology inc. 2.2 programmer?s model the programmer?s model is shown in figure 2-1 and consists of 16x16-bit working registers (w0 through w15), 2x40-bit accumulators (acca and accb), status register (sr), data table page register (tblpag), program space visibility page register (psvpag), do and repeat registers (dostart, doend, dcount and rco unt), and program counter (pc). the working r egisters can act as data, address or offset registers. all registers are memory mapped. w0 acts as the w register for file register addressing. some of these registers have a shadow register asso- ciated with each of them, as shown in figure 2-1. the shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. none of the shadow registers are accessible directly. the following rules apply for transfer of regist ers into and out of shadows. push.s and pop.s w0, w1, w2, w3, sr (dc, n, ov, z and c bits only) are transferred. do instruction dostart, doend, dcount shadows are pushed on loop start, and popped on loop end. when a byte operation is performed on a working reg- ister, only the least significant byte of the target regis- ter is affected. however, a benefit of memory mapped working registers is that both the least and most significant bytes can be manipulated through byte wide data memory space accesses. 2.2.1 software stack pointer/ frame pointer the dspic ? devices contain a software stack. w15 is the dedicated software stac k pointer (sp), and will be automatically modified by exception processing and subroutine calls and returns. however, w15 can be ref- erenced by any instruction in the same manner as all other w registers. this simpli fies the reading, writing and manipulation of the stac k pointer (e.g., creating stack frames). w15 is initialized to 0x0800 during a reset. the user may reprogram the sp duri ng initialization to any location within data space. w14 has been dedicated as a stack frame pointer as defined by the lnk and ulnk instructions. however, w14 can be referenced by any instruction in the same manner as all other w registers. 2.2.2 status register the dspic core has a 16-bit status register (sr), the ls byte of which is referred to as the sr low byte (srl) and the ms byte as the sr high byte (srh). see figure 2-1 for sr layout. srl contains all the mcu al u operation status flags (including the z bit), as well as the cpu interrupt prior- ity level status bits, ipl<2:0>, and the repeat active status bit, ra. during exception processing, srl is concatenated with the ms byte of the pc to form a complete word value wh ich is then stacked. the upper byte of the sr register contains the dsp adder/subtractor status bits, the do loop active bit (da) and the digit carry (dc) status bit. 2.2.3 program counter the program counter is 23 bits wide. bit 0 is always clear. therefore, the pc can address up to 4m instruction words. note: in order to protect against misaligned stack accesses, w15< 0> is always clear.
? 2005 microchip technology inc. preliminary ds70135c-page 17 DSPIC30F4011/4012 figure 2-1: DSPIC30F4011/4012 programmer?s model tabpag pc22 pc0 7 0 d0 d15 program counter data table page address status register working registers dsp operand registers w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12/dsp offset w13/dsp write back w14/frame pointer w15/stack pointer dsp address registers ad39 ad0 ad31 dsp accumulators acca accb psvpag 7 0 program space visibility page address z 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter dostart 22 0 do loop start address ipl2 ipl1 splim stack pointer limit register ad15 srl push.s shadow do shadow oab sab 15 0 core configuration register legend corcon da dc ra n tblpag psvpag ipl0 ov w0/wreg srh do loop end address doend 22 c
DSPIC30F4011/4012 ds70135c-page 18 preliminary ? 2005 microchip technology inc. 2.3 divide support the dspic devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iter ative divides. the following instructions and data sizes are supported: 1. divf ? 16/16 signed fractional divide 2. div.sd ? 32/16 signed divide 3. div.ud ? 32/16 unsigned divide 4. div.sw ? 16/16 signed divide 5. div.uw ? 16/16 unsigned divide the divide instructions must be executed within a repeat loop. any other form of execution (e.g. a series of discrete divide instructions) will not function correctly because the instruction flow depends on rcount. the divide instruction does not automatically set up the rcount value, and it must, therefore, be explicitly and correctly specified in the repeat instruction, as shown in table 2-1 ( repeat will execute the target instruction {operand value+1} times). the repeat loop count must be set up for 18 iterations of the div/divf instruction. thus, a complete divide operation requires 19 cycles. table 2-1: divide instructions 2.4 dsp engine the dsp engine consists of a high speed 17-bit x 17-bit multiplier, a barrel shifter, and a 40-bit adder/ subtractor (with two target accumulators, round and saturation logic). the dspic30f devices have a single instruction flow which can execute either dsp or mcu instructions. many of the hardware resources are shared between the dsp and mcu instruct ions. for example, the instruction set has both dsp and mcu multiply instructions which use the same hardware multiplier. the dsp engine also has the capability to perform inher- ent accumulator-to-accumulator operations, which require no additional data. these instructions are add, sub and neg . the dsp engine has various options selected through various bits in the cpu core configuration register (corcon), as listed below: 1. fractional or integer dsp multiply (if). 2. signed or unsigne d dsp multiply (us). 3. conventional or convergent rounding (rnd). 4. automatic saturation on/off for acca (sata). 5. automatic saturation on/off for accb (satb). 6. automatic saturation on /off for writes to data memory (satdw). 7. accumulator saturation mode selection (accsat). a block diagram of the dsp engine is shown in figure 2-2. note: the divide flow is interruptible. however, the user needs to save the context as appropriate. instruction function divf signed fractional divide: wm/wn w0; rem w1 div.sd signed divide: (wm+1:wm)/wn w0; rem w1 div.sw (or div.s) signed divide: wm/wn w0; rem w1 div.ud unsigned divide: (wm+1:wm)/wn w0; rem w1 div.uw (or div.u) unsigned divide: wm/wn w0; rem w1 note: for corcon layout, see table 4-2. table 2-2: dsp instruction summary instruction algebraic operation clr a = 0 ed a = (x ? y) 2 edac a = a + (x ? y) 2 mac a = a + (x * y) movsac no change in a mpy a = x * y mpy.n a = ? x * y msc a = a ? x * y
? 2005 microchip technology inc. preliminary ds70135c-page 19 DSPIC30F4011/4012 figure 2-2: dsp engine block diagram zero backfill sign-extend barrel shifter 40-bit accumulator a 40-bit accumulator b round logic x data bus to/from w array adder saturate negate 32 32 33 16 16 16 16 40 40 40 40 s a t u r a t e y data bus 40 carry/borrow out carry/borrow in 16 40 multiplier/scaler 17-bit
DSPIC30F4011/4012 ds70135c-page 20 preliminary ? 2005 microchip technology inc. 2.4.1 multiplier the 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (q31) or 32-bit integer results. unsigned operands are ze ro-extended into the 17th bit of the multiplier input value. signed operands are sign-extended in to the 17th bit of the mul- tiplier input value. the output of the 17x17-bit multiplier/ scaler is a 33-bit value, which is sign-extended to 40 bits. integer data is inherent ly represented as a signed two?s complement value, where the msb is defined as a sign bit. generally speaking, the range of an n-bit two?s complement integer is -2 n-1 to 2 n-1 ? 1. for a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7fff), including 0. for a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7fff ffff). when the multiplier is confi gured for fractional multipli- cation, the data is repres ented as a two?s complement fraction, where the msb is defined as a sign bit and the radix point is implied to lie just after the sign bit (qx format). the range of an n-bit two?s complement fraction with this implied radix point is -1.0 to (1-2 1-n ). for a 16-bit fraction, the q15 data range is -1.0 (0x8000) to 0.999969482 (0 x7fff), including 0 and has a precision of 3.01518x10 -5 . in fractional mode, a 16x16 multiply operation generates a 1.31 product, which has a precision of 4.65661x10 -10 . the same multiplier is used to support the mcu multi- ply instructions, which in clude integer 16-bit signed, unsigned and mixe d sign multiplies. the mul instruction may be directed to use byte or word sized operands. byte op erands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the w array. 2.4.2 data accumulators and adder/subtractor the data accumulator consists of a 40-bit adder/ subtractor with automatic sign extension logic. it can select one of two accumulators (a or b) as its pre- accumulation source and post-accumulation destina- tion. for the add and lac instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. 2.4.2.1 adder/subtractor, overflow and saturation the adder/subtractor is a 40- bit adder with an optional zero input into one side and either true or complement data into the other input. in the case of addition, the carry/borrow input is active high and the other input is true data (not complemented ), whereas in the case of subtraction, the carry/borrow input is active low and the other input is complement ed. the adder/subtractor generates overflow status bits sa/sb and oa/ob, which are latched and reflect ed in the status register. overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. overflow into guard bits 32 through 39: this is a recoverable overflow. this bit is set whenever all the guard bits are not identical to each other. the adder has an additiona l saturation block which controls accumulator data saturation, if selected. it uses the result of the adder, the overflow status bits described above, and the sata/b (corcon<7:6>) and accsat (corcon<4>) mode control bits to determine when and to what value to saturate. six status register bits hav e been provided to support saturation and overflow; they are: 1. oa: acca overflowed into guard bits 2. ob: accb overflowed into guard bits 3. sa: acca saturated (bit 31 overflow and saturation) or acca overflowed into gua rd bits and saturated (bit 39 overflow and saturation) 4. sb: accb saturated (bit 31 overflow and saturation) or accb overflowed into gua rd bits and saturated (bit 39 overflow and saturation) 5. oab: logical or of oa and ob 6. sab: logical or of sa and sb the oa and ob bits are modified each time data passes through the adder/su btractor. when set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). the oa and ob bits can a lso optionally generate an arithmetic warning trap w hen set and the correspond- ing overflow trap flag en able bit (ovaten, ovbten) in the intcon1 register (refer to section 5.0) is set. this allows the user to take i mmediate action, for example, to correct system gain.
? 2005 microchip technology inc. preliminary ds70135c-page 21 DSPIC30F4011/4012 the sa and sb bits are modified each time data passes through the adder/subtractor, but can only be cleared by the user. when set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit sat- uration, or bit 39 for 40-bit saturation) and will be satu- rated (if saturation is enabled). when saturation is not enabled, sa and sb default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. if the covte bit in the intcon1 register is set, sa and sb bits will generate an arithmetic warning trap when satu- ration is disabled. the overflow and saturation status bits can optionally be viewed in the status regi ster (sr) as the logical or of oa and ob (in bit oab) an d the logical or of sa and sb (in bit sab). this allows programmers to check one bit in the status register to determine if either accumu- lator has overflowed, or one bit to determine if either accumulator has saturated. this would be useful for complex number arithmetic which typically uses both the accumulators. the device supports three saturation and overflow modes. 1. bit 39 overflow and saturation: when bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7fffffffff) or maximally negative 9.31 value (0x8000000000) into the target accumula- tor. the sa or sb bit is set and remains set until cleared by the user. this is referred to as ?super saturation? and provides protection against erro- neous data or unexpected algorithm problems (e.g., gain calculations). 2. bit 31 overflow and saturation: when bit 31 overflow and saturation occurs, the saturation logic then lo ads the maximally posi- tive 1.31 value (0x007fffffff) or maximally negative 1.31 value (0x0080000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user. when this saturation mode is in effect, the guard bits are not used (so the oa, ob or oab bits are never set). 3. bit 39 catastrophic overflow the bit 39 overflow status bit from the adder is used to set the sa or sb bit, which remain set until cleared by the user. no saturation operation is performed and the accu mulator is allowed to overflow (destroying its sign). if the covte bit in the intcon1 register is set, a catastrophic overflow can initiate a trap exception. 2.4.2.2 accumulator ?write back? the mac class of instructions (with the exception of mpy, mpy.n, ed and edac ) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. the write is performed across the x bus into combined x and y address space. the following addressing modes are supported: 1. w13, register direct: the rounded contents of the non-target accumula- tor are written into w13 as a 1.15 fraction. 2. [w13]+=2, register indirect with post-increment: the rounded contents of the non-target accumu- lator are written into th e address pointed to by w13 as a 1.15 fraction. w13 is then incremented by 2 (for a word write). 2.4.2.3 round logic the round logic is a combinational block, which per- forms a conventional (biased) or convergent (unbiased) round function during an accu mulator write (store). the round mode is determined by the state of the rnd bit in the corcon register. it generates a 16-bit, 1.15 data value which is passed to t he data space write saturation logic. if rounding is not indica ted by the instruction, a truncated 1.15 data value is stored and the ls word is simply discarded. conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the accxh word (bits 16 through 31 of the accumulator). if the accxl word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xffff (0x8000 include d), accxh is incre- mented. if accxl is between 0x0000 and 0x7fff, accxh is left unchanged. a consequence of this algo- rithm is that over a succession of random rounding operations, the value will tend to be biased slightly positive. convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when accxl equals 0x8000. if this is the case, the ls bit (bit 16 of the accumulator) of a ccxh is examined. if it is ? 1 ?, accxh is incremented. if it is ? 0 ?, accxh is not modi- fied. assuming that bit 16 is effectively random in nature, this scheme will remo ve any rounding bias that may accumulate. the sac and sac.r instructions store either a trun- cated ( sac ) or rounded ( sac.r ) version of the contents of the target accumulator to data memory, via the x bus (subject to data saturation, see section 2.4.2.4). note that for the mac class of instructions, the accumulator write back operation will function in the same manner, addressing combined mcu (x and y) data space though the x bus. for this cla ss of instructions, the data is always subject to rounding.
DSPIC30F4011/4012 ds70135c-page 22 preliminary ? 2005 microchip technology inc. 2.4.2.4 data space write saturation in addition to adder/subtractor saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. the data space write saturation logic block accepts a 16-bit, 1.15 frac- tional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. these are combined and used to select the appropriate 1.15 frac- tional value as output to wr ite to data space memory. if the satdw bit in the corcon register is set, data (after rounding or truncation ) is tested for overflow and adjusted accordingly. for input data greater than 0x007fff, data written to me mory is forced to the max- imum positive 1.15 value, 0x7fff. for input data less than 0xff8000, data written to memory is forced to the maximum negative 1.15 valu e, 0x8000. the ms bit of the source (bit 39) is used to determine the sign of the operand being tested. if the satdw bit in the corco n register is not set, the input data is always pass ed through unmodified under all conditions. 2.4.3 barrel shifter the barrel shifter is capabl e of performing up to 16-bit arithmetic or logic right shifts , or up to 16-bit left shifts in a single cycle. the source can be either of the two dsp accumulators or the x bus (to support multi-bit shifts of register or memory data). the shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. a positive value will shift the operand right. a negative value will shift the operand left. a value of 0 will not modify the operand. the barrel shifter is 40 bi ts wide, thereby obtaining a 40-bit result for dsp shift op erations and a 16-bit result for mcu shift operations. data from the x bus is pre- sented to the barrel shifter between bit positions 16 to 31 for right shifts, a nd bit positions 0 to 15 for left shifts.
? 2005 microchip technology inc. preliminary ds70135c-page 23 DSPIC30F4011/4012 3.0 memory organization 3.1 program address space the program address space is 4m instruction words. it is addressable by the 23-bit pc, table instruction effective address (ea), or data space ea, when program space is mapped into data space, as defined by table 3-1. note that th e program space address is incremented by two betw een successive program words, in order to provide compatibility with data space addressing. user program space access is restricted to the lower 4m instruction word a ddress range (0x000000 to 0x7ffffe), for all ac cesses other than tblrd/tblwt , which use tblpag<7> to deter mine user or configura- tion space access. in table 3-1, read/write instruc- tions, bit 23 allows access to the device id, the user id and the configuration bits . otherwise, bit 23 is always clear. figure 3-1: program space memory map for DSPIC30F4011/4012 note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). reset - target address user memory space 000000 00007e 000002 000080 device configuration user flash program memory 008000 007ffe configuration memory space data eeprom (16k instructions) (1 kbytes) 800000 f80000 registers f8000e f80010 devid (2) fefffe ff0000 fffffe reserved f7fffe reserved 7ffc00 7ffbfe (read 0?s) 8005fe 800600 unitid (32 instr.) 8005be 8005c0 reset - goto instruction 000004 reserved 7ffffe reserved 000100 0000fe 000084 alternate vector table reserved interrupt vector table vector tables
DSPIC30F4011/4012 ds70135c-page 24 preliminary ? 2005 microchip technology inc. table 3-1: program space address construction figure 3-2: data access from program space address generation access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access user 0 pc<22:1> 0 tblrd/tblwt user (tblpag<7> = 0 ) tblpag<7:0> data ea <15:0> tblrd/tblwt configuration (tblpag<7> = 1 ) tblpag<7:0> data ea <15:0> program space visibility user 0 psvpag<7:0> data ea <14:0> 0 program counter 23 bits 1 psvpag reg 8 bits ea 15 bits program using select tblpag reg 8 bits ea 16 bits using byte 24-bit ea 0 0 1/0 select user/ configuration table instruction program space counter using space select note: program space visibility cannot be used to access bits <23:16> of a word in program memory. visibility
? 2005 microchip technology inc. preliminary ds70135c-page 25 DSPIC30F4011/4012 3.1.1 data access from program memory using table instructions this architecture fetches 24-bit wide program memory. consequently, instructions are always aligned. how- ever, as the architecture is modified harvard, data can also be present in program space. there are two methods by which program space can be accessed; via special table instructions, or through the remapping of a 16k word program space page into the upper half of data spac e (see section 3.1.2). the tblrdl and tblwtl instructions offer a direct method of reading or writing the ls word of any address within program space, without going through data space. the tblrdh and tblwth instructions are the only method whereby the upper 8 bits of a program space word can be accessed as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space which cont ains the ls data word, and tblrdh and tblwth access the space which contains the ms data byte. figure 3-2 shows how the ea is created for table oper- ations and data space accesses (psv = 1 ). here, p<23:0> refers to a program space word, whereas d<15:0> refers to a data space word. a set of table instructions are provided to move byte or word sized data to and from program space. 1. tblrdl: table read low word: read the ls word of the program address; p<15:0> maps to d<15:0>. byte: read one of the ls bytes of the program address; p<7:0> maps to the destination byte when byte select = 0 ; p<15:8> maps to the destination byte when byte select = 1 . 2. tblwtl: table write low (refer to section 6.0 for details on flash programming). 3. tblrdh: table read high word: read the ms word of the program address; p<23:16> maps to d<7:0>; d<15:8> always be = 0 . byte: read one of the ms bytes of the program address; p<23:16> maps to the destination byte when byte select = 0 ; the destination byte will always be = 0 when byte select = 1 . 4. tblwth: table write high (refer to section 6.0 for details on flash programming). figure 3-3: program data table access (ls word) 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?). tblrdl.w tblrdl.b (wn<0> = 1) tblrdl.b (wn<0> = 0)
DSPIC30F4011/4012 ds70135c-page 26 preliminary ? 2005 microchip technology inc. figure 3-4: program data table access (ms byte) 3.1.2 data access from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into any 16k word program space page. this provides transparent access of stored constant data from x data space, without the need to use special instructions (i.e., tblrdl/h, tblwtl/h instructions). program space access through the data space occurs if the ms bit of the data space ea is set and program space visibility is enabled, by setting the psv bit in the core control register (corcon). the functions of corcon are discussed in section 2.4, dsp engine. data accesses to this area add an additional cycle to the instruction being exec uted, since two program memory fetches are required. note that the upper half of addressable data space is always part of the x data space. therefore, when a dsp operation uses program space mapping to access this memory region, y data sp ace should typically con- tain state (variable) data for dsp operations, whereas x data space should typically contain coefficient (constant) data. although each data space address, 0x8000 and higher, maps directly into a co rresponding program memory address (see figure 3-5), only the lower 16-bits of the 24-bit program word are used to contain the data. the upper 8 bits should be progr ammed to force an illegal instruction to maintain machine robustness. refer to the dspic30f programmer?s reference manual (ds70030) for details on instruction encoding. note that by incrementing the pc by 2 for each pro- gram memory word, the ls 15 bits of data space addresses directly map to the ls 15 bits in the corre- sponding program space addresses. the remaining bits are provided by the program space visibility page register, psvpag<7:0>, as shown in figure 3-5. for instructions that use psv which are executed outside a repeat loop: the following instructions will require one instruc- tion cycle in addition to the specified execution time: - mac class of instructions with data operand pre-fetch - mov instructions - mov.d instructions all other instructions will require two instruction cycles in addition to the specified execution time of the instruction. for instructions that use psv which are executed inside a repeat loop: the following instances w ill require two instruction cycles in addition to the specified execution time of the instruction: - execution in the first iteration - execution in the last iteration - execution prior to exiting the loop due to an interrupt - execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop will allow the instruction, accessing data using psv, to execute in a single cycle. 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) tblrdh.w tblrdh.b (wn<0> = 1) tblrdh.b (wn<0> = 0) note: psv access is temporarily disabled during table reads/writes.
? 2005 microchip technology inc. preliminary ds70135c-page 27 DSPIC30F4011/4012 figure 3-5: data space window into program space operation 3.2 data address space the core has two data spaces. the data spaces can be considered either separate (for some dsp instruc- tions), or as one unified li near address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. 3.2.1 data space memory map the data space memory is split into two blocks, x and y data space. a key element of this architecture is that y space is a subset of x space, and is fully contained within x space. in order to provide an apparent linear addressing space, x and y spaces have contiguous addresses. when executing any instructio n other than one of the mac class of instructions, the x block consists of the 64 kbyte data address space (i ncluding all y addresses). when executing one of the mac class of instructions, the x block consists of the 64 kbyte data address space excluding the y address block (for data reads only). in other words, all ot her instructions regard the entire data memory as one composite address space. the mac class instructions extract the y address space from data space and address it using eas sourced from w10 and w11. the remaining x data space is addressed using w8 and w9. both address spaces are concurrently accessed only with the mac class instructions. a data space memory map is shown in figure 3-6. figure 3-7 shows a graphical summary of how x and y data spaces are accessed for mcu and dsp instructions. 23 15 0 psvpag (1) 15 15 ea<15> = 0 ea<15> = 1 16 data space ea data space program space 8 15 23 0x0000 0x8000 0xffff 0x00 0x000100 0x007ffe data read upper half of data space is mapped into program space note: psvpag is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper ha lf of data space is being mapped). 0x001200 address concatenation bset corcon,#2 ; psv bit set mov #0x00, w0 ; set psvpag register mov w0, psvpag mov 0x9200, w0 ; access program memory location ; using a data space access
DSPIC30F4011/4012 ds70135c-page 28 preliminary ? 2005 microchip technology inc. figure 3-6: DSPIC30F4011/4012 data space memory map 0x0000 0x07fe 0x0bfe 0xfffe ls byte address 16 bits lsb msb ms byte address 0x0001 0x07ff 0x0bff 0xffff 0x8001 0x8000 optionally mapped into program memory 0x0fff 0x0ffe 0x1000 0x1001 0x0801 0x0800 0x0c01 0x0c00 near data 2 kbyte sfr space 2 kbyte sram space 4096 bytes space unimplemented (x) x data sfr space x data ram (x) y data ram (y)
? 2005 microchip technology inc. preliminary ds70135c-page 29 DSPIC30F4011/4012 figure 3-7: data space for mcu and dsp ( mac class) instructions example sfr space (y space) x space sfr space unused x space x space y space unused unused non- mac class ops (read/write) mac class ops read only indirect ea using any w indirect ea us ing w8, w9 indirect ea using w10, w11 mac class ops (write)
DSPIC30F4011/4012 ds70135c-page 30 preliminary ? 2005 microchip technology inc. 3.2.2 data spaces the x data space is used by all instructions and sup- ports all addressing modes. there are separate read and write data buses. the x read data bus is the return data path for all instructio ns that view data space as combined x and y address space. it is also the x address space data path for the dual operand read instructions ( mac class). the x write data bus is the only write path to data space for all instructions. the x data space also supp orts modulo addressing for all instructions, subject to addressing mode restric- tions. bit-reversed addres sing is only supported for writes to x data space. the y data space is used in concert with the x data space by the mac class of instructions ( clr, ed, edac, mac, movsac, mpy, mpy.n and msc ) to pro- vide two concurrent data read paths. no writes occur across the y bus. this class of instructions dedicates two w register pointers, w10 and w11, to always address y data space, independent of x data space, whereas w8 and w9 always address x data space. note that during accumulator write back, the data address space is considered a combination of x and y data spaces, so the write occurs across the x bus. consequently, the write can be to any address in the entire data space. the y data space can only be used for the data pre- fetch operation associated with the mac class of instructions. it also sup ports modulo addressing for automated circular buffers. of course, all other instruc- tions can access the y data address space through the x data path, as part of the composite linear space. the boundary between the x and y data spaces is defined as shown in figure 3-6 and is not user pro- grammable. should an ea po int to data outside its own assigned address space, or to a location outside phys- ical memory, an all-zero word/byte will be returned. for example, although y addres s space is visible by all non- mac instructions using any addressing mode, an attempt by a mac instruction to fetch data from that space, using w8 or w9 (x space pointers), will return 0x0000. all effective addresses are 16 bits wide and point to bytes within the data space. therefore, the data space address range is 64 kbytes or 32k words. 3.2.3 data space width the core data width is 16-bits . all internal registers are organized as 16-bit wide word s. data space memory is organized in byte addressa ble, 16-bit wide blocks. 3.2.4 data alignment to help maintain backward compatibility with picmicro ? devices and improve data space memory usage efficiency, the dspic30f instruction set supports both word and byte operations. data is aligned in data memory and registers as word s, but all data space eas resolve to bytes. data byte reads will read the complete word, which contains the byte , using the ls bit of any ea to determine which byte to select. the selected byte is placed onto the ls byte of the x data path (no byte accesses are possible from the y data path as the mac class of instruction can only fetch words). that is, data memory and registers are organized as two parallel byte wide entities with s hared (word) address decode, but separate write lines. data byte writes only write to the corresponding side of t he array or register which matches the byte address. as a consequence of this byte accessibility, all effective address calculations (includi ng those generated by the dsp operations, which are restricted to word sized data) are internally scaled to step through word aligned memory. for example, the core would recognize that post-modified register indirect addressing mode, [ws++], will result in a value of ws+1 for byte operations and ws+2 fo r word operations. all word accesses must be al igned to an even address. mis-aligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit mcu code. should a mis- aligned read or write be a ttempted, an address error trap will be generated. if the error occurred on a read, the instruction underway is completed, whereas if it occurred on a write, the inst ruction will be executed but the write will not occur. in either case, a trap will then be executed, allowing the syst em and/or user to exam- ine the machine state prior to execution of the address fault. figure 3-8: data alignment table 3-2: effect of invalid memory accesses attempted operation data returned ea = an unimplemented address 0x0000 w8 or w9 used to access y data space in a mac instruction 0x0000 w10 or w11 used to access x data space in a mac instruction 0x0000 15 8 7 0 0001 0003 0005 0000 0002 0004 byte 1 byte 0 byte 3 byte 2 byte 5 byte 4 ls byte ms byte
? 2005 microchip technology inc. preliminary ds70135c-page 31 DSPIC30F4011/4012 all byte loads into any w re gister are loaded into the ls byte. the msb is not modified. a sign-extend ( se ) instruction is provided to allow users to translate 8-bit si gned data to 16-bit signed values. alternatively, for 16 -bit unsigned data, users can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions, including t he dsp instructions, operate only on words. 3.2.5 near data space an 8 kbyte ?near? data spac e is reserved in x address memory space between 0x0000 and 0x1fff, which is directly addressable via a 13-b it absolute address field within all memory direct in structions. the remaining x address space and all of the y address space is addressable indirectly. additionally, the whole of x data space is addressable using mov instructions, which support memory direct addressing with a 16-bit address field. 3.2.6 software stack the dspic device contains a software stack. w15 is used as the stack pointer. the stack pointer always points to the first available free word and grows from lower addresses towards higher addresses. it pre-dec rements for stack pops and post-increments for stac k pushes, as shown in figure 3-9. note that for a pc push during any call instruction, the msb of t he pc is zero-extended before the push, ensuring that the msb is always clear. there is a stack pointer limit register (splim) associ- ated with the stack pointe r. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to ? 0 ?, because all stack operations must be word aligned. whenever an effective address (ea) is generated using w15 as a source or destination pointer, the address thus generated is compared with the value in splim. if the cont ents of the stack pointer (w15) and the splim regist er are equal and a push operation is performed, a st ack error trap will not occur. the stack error trap will occur on a subsequent push operation. thus, for exam ple, if it is desirable to cause a stack error trap when the stack grows beyond address 0x2000 in ram, initia lize the splim with the value, 0x1ffe. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0x0800, thus preventing the stack from interfering with the specia l function register (sfr) space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 3-9: call stack frame note: a pc push during exception processing will concatenate the srl register to the msb of the pc prior to the push. pc<15:0> 000000000 0 15 w15 (before call ) w15 (after call ) stack grows towards higher address push: [w15++] pop: [--w15] 0x0000 pc<22:16>
DSPIC30F4011/4012 ds70135c-page 32 preliminary ? 2005 microchip technology inc. table 3-3: core register map sfr name address (home) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 reset state w0 0000 w0 / wreg 0000 0000 0000 0000 w1 0002 w1 0000 0000 0000 0000 w2 0004 w2 0000 0000 0000 0000 w3 0006 w3 0000 0000 0000 0000 w4 0008 w4 0000 0000 0000 0000 w5 000a w5 0000 0000 0000 0000 w6 000c w6 0000 0000 0000 0000 w7 000e w7 0000 0000 0000 0000 w8 0010 w8 0000 0000 0000 0000 w9 0012 w9 0000 0000 0000 0000 w10 0014 w10 0000 0000 0000 0000 w11 0016 w11 0000 0000 0000 0000 w12 0018 w12 0000 0000 0000 0000 w13 001a w13 0000 0000 0000 0000 w14 001c w14 0000 0000 0000 0000 w15 001e w15 0000 1000 0000 0000 splim 0020 splim 0000 0000 0000 0000 accal 0022 accal 0000 0000 0000 0000 accah 0024 accah 0000 0000 0000 0000 accau 0026 sign-extension (acca<39>) accau 0000 0000 0000 0000 accbl 0028 accbl 0000 0000 0000 0000 accbh 002a accbh 0000 0000 0000 0000 accbu 002c sign-extension (accb<39>) accbu 0000 0000 0000 0000 pcl 002e pcl 0000 0000 0000 0000 pch 0030 ? ? ? ? ? ? ? ? ?pch 0000 0000 0000 0000 tblpag 0032 ? ? ? ? ? ? ? ? tblpag 0000 0000 0000 0000 psvpag 0034 ? ? ? ? ? ? ? ?psvpag 0000 0000 0000 0000 rcount 0036 rcount uuuu uuuu uuuu uuuu dcount 0038 dcount uuuu uuuu uuuu uuuu dostartl 003a dostartl 0 uuuu uuuu uuuu uuu0 dostarth 003c ? ? ? ? ? ? ? ? ? dostarth 0000 0000 0uuu uuuu doendl 003e doendl 0 uuuu uuuu uuuu uuu0 doendh 0040 ? ? ? ? ? ? ? ? ? doendh 0000 0000 0uuu uuuu sr 0042 oa ob sa sb oab sab da dc ipl2 ipl1 ipl0 ra n ov z c 0000 0000 0000 0000 corcon 0044 ? ? ? us edt dl2 dl1 dl0 sata satb satdw accsat ipl3 psv rnd if 0000 0000 0010 0000 modcon 0046 xmoden ymoden ? ? bwm<3:0> ywm<3:0> xwm<3:0> 0000 0000 0000 0000 legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 33 DSPIC30F4011/4012 note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. xmodsrt 0048 xs<15:1> 0 uuuu uuuu uuuu uuu0 xmodend 004a xe<15:1> 1 uuuu uuuu uuuu uuu1 ymodsrt 004c ys<15:1> 0 uuuu uuuu uuuu uuu0 ymodend 004e ye<15:1> 1 uuuu uuuu uuuu uuu1 xbrev 0050 bren xb<14:0> uuuu uuuu uuuu uuuu disicnt 0052 ? ? disicnt<13:0> 0000 0000 0000 0000 table 3-3: core register map (continued) sfr name address (home) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 reset state legend: u = uninitialized bit
DSPIC30F4011/4012 ds70135c-page 34 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 35 DSPIC30F4011/4012 4.0 address generator units the dspic core contains two independent address generator units: the x ag u and y agu. the y agu supports word sized data reads for the dsp mac class of instructions only. the dspic agus support three types of data addressing: linear addressing modulo (circular) addressing bit-reversed addressing linear and modulo data addressing modes can be applied to data space or program space. bit-reversed addressing is only applicable to data space addresses. 4.1 instruction addressing modes the addressing modes in table 4-1 form the basis of the addressing modes optimiz ed to support the specific features of individual in structions. the addressing modes provided in the mac class of instructions are somewhat different from those in the other instruction types. 4.1.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions empl oy a working register w0, which is denoted as wreg in these instructions. the destination is typically either the same file register, or wreg (with the exception of the mul instruction), which writes the result to a r egister or register pair. the mov instruction allows additi onal flexibility and can access the entire data space during file register operation. 4.1.2 mcu instructions the three-operand mcu instructions are of the form: operand 3 = operand 1 operand 2 where operand 1 is always a working register (i.e., the addressing mode can only be register direct), which is referred to as wb. operand 2 can be a w register, fetched from data memory, or a 5-bit literal. the result location can be either a w register or an address location. the following addressing modes are supported by mcu instructions: register direct register indirect register indirect post-modified register indirect pre-modified 5-bit or 10-bit literal table 4-1: fundamental addressing modes supported note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). note: not all instructions su pport all the address- ing modes given above. individual instructions may support different subsets of these addressing modes. addressing mode description file register direct the address of th e file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn forms the ea. register indirect post-modified the contents of wn forms the ea. wn is pos t-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (incre mented or decremented) by a signed constant value to form the ea. register indirect with register offs et the sum of wn and wb forms the ea. register indirect with literal offset t he sum of wn and a li teral forms the ea.
DSPIC30F4011/4012 ds70135c-page 36 preliminary ? 2005 microchip technology inc. 4.1.3 move and accumulator instructions move instructions and the dsp accumulator class of instructions provide a great er degree of addressing flexibility than other instru ctions. in addition to the addressing modes supported by most mcu instruc- tions, move and accumulator in structions also support register indirect with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: register direct register indirect register indirect post-modified register indirect pre-modified register indirect with register offset (indexed) register indirect with literal offset 8-bit literal 16-bit literal 4.1.4 mac instructions the dual source operand dsp instructions ( clr, ed, edac, mac, mpy, mpy.n, movsac and msc ), also referred to as mac instructions, utilize a simplified set of addressing modes to allow the user to effectively manipulate the data pointers through register indirect tables. the two source operand pre-fe tch registers must be a member of the set {w8, w9, w10, w11}. for data reads, w8 and w9 will al ways be directed to the x ragu and w10 and w11 will al ways be directed to the y agu. the effective addresses generated (before and after modification) must, ther efore, be valid addresses within x data space for w8 and w9 and y data space for w10 and w11. in summary, the followin g addressing modes are supported by the mac class of instructions: register indirect register indirect post-modified by 2 register indirect post-modified by 4 register indirect post-modified by 6 register indirect with register offset (indexed) 4.1.5 other instructions besides the various addres sing modes outlined above, some instructions use litera l constants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as add acc , the source of an operand or re sult is implied by the opcode itself. certain operations, such as nop , do not have any operands. 4.2 modulo addressing modulo addressing is a me thod of providing an auto- mated means to support circ ular data buffers using hardware. the objective is to remove the need for soft- ware to perform data address boundary checks when executing tightly looped co de, as is typical in many dsp algorithms. modulo addressing can operate in either data or pro- gram space (since the data pointer mechanism is essen- tially the same for both). one circular buffer can be supported in each of the x (which also provides the pointers into program space) and y data spaces. mod- ulo addressing can operate on any w register pointer. however, it is not advisable to use w14 or w15 for mod- ulo addressing, since these two registers are used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can only be configured to operate in one direction, as there are cer- tain restrictions on the buffer start address (for incre- menting buffers) or end address (for decrementing buffers) based upon the direction of the buffer. the only exception to the usage restrictions is for buff- ers which have a power-of- 2 length. as these buffers satisfy the start and end add ress criteria, they may operate in a bi-directional mode, (i.e., address bound- ary checks will be performed on both the lower and upper address boundaries). note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. how- ever, the 4-bit wb (register offset) field is shared between both source and destination (but typically only used by one). note: not all instructions support all the address- ing modes given ab ove. individual instructions may support different subsets of these addressing modes. note: register indirect with register offset addressing is only available for w9 (in x space) and w11 (in y space).
? 2005 microchip technology inc. preliminary ds70135c-page 37 DSPIC30F4011/4012 4.2.1 start and end address the modulo addressing scheme requires that a starting and an end address be specified and loaded into the 16-bit modulo bu ffer address registers: xmodsrt, xmodend, ymodsrt and ymodend (see table 3-3).. the length of a circular buffer is not directly specified. it is determined by the difference between the corre- sponding start and end addr esses. the maximum pos- sible length of the circular buffer is 32k words (64 kbytes). 4.2.2 w address register selection the modulo and bit-reversed addressing control reg- ister modcon<15:0> contains enable flags as well as a w register field to spec ify the w address registers. the xwm and ywm fields select which registers will operate with modul o addressing. if xwm = 15, x ragu and x wagu modulo addre ssing are disabled. simi- larly, if ywm = 15, y agu modulo addressing is disabled. the x address space pointer w register (xwm) to which modulo addressing is to be applied, is stored in modcon<3:0> (see table 3- 3). modulo addressing is enabled for x data space when xwm is set to any value other than 15 and the xmoden bit is set at modcon<15>. the y address space pointer w register (ywm) to which modulo addressing is to be applied, is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than 15 and the ymoden bit is set at modcon<14>. figure 4-1: modulo addressing operation example note: y-space modulo addressing ea calcula- tions assume word-sized data (ls bit of every ea is always clear). 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100,w0 mov w0, xmodsrt ;set mo dulo start address mov #0x1163,w0 mov w0,modend ;set mo dulo end address mov #0x8001,w0 mov w0,modcon ;enable w1 , x agu for modulo mov #0x0000,w0 ;w0 hol ds buffer fill value mov #0x1110,w1 ;point w1 to buffer do again,#0x31 ;fill t he 50 buffer locations mov w0, [w1++] ;fill the next location again: inc w0,w0 ;increm ent the fill value
DSPIC30F4011/4012 ds70135c-page 38 preliminary ? 2005 microchip technology inc. 4.2.3 modulo addressing applicability modulo addressing can be ap plied to the effective address (ea) calculation as sociated with any w regis- ter. it is important to re alize that the address bound- aries check for addresses less than or greater than the upper (for incrementing buff ers) and lower (for decre- menting buffers) boundary ad dresses (not just equal to). address changes may, therefore, jump beyond boundaries and still be adjusted correctly. 4.3 bit-reversed addressing bit-reversed addressing is intended to simplify data re- ordering for radix- 2 fft algorithms. it is supported by the x agu for data writes only. the modifier, which may be a constant value or register contents, is regarded as having its bit order reversed. the address source and desti nation are kept in normal order. thus, the only operan d requiring reversal is the modifier. 4.3.1 bit-reversed addressing implementation bit-reversed addressing is enabled when: 1. bwm (w register selection) in the modcon register is any value other than 15 (the stack can not be accessed using bit-reversed addressing) and 2. the bren bit is set in the xbrev register and 3. the addressing mode used is register indirect with pre-increment or post-increment. if the length of a bit-reversed buffer is m = 2 n bytes, then the last ?n? bits of th e data buffer start address must be zeros. xb<14:0> is the bit-reversed address modifier or ?pivot point? which is typically a co nstant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing will only be executed for register indi rect with pre-increment or post-increment addressing and word sized data writes. it will not function for any ot her addressing mode or for byte-sized data, and normal addresses will be gener- ated instead. when bit-re versed addressing is active, the w address pointer will always be added to the address modifier (xb) and the offset associated with the register indirect addressing mode will be ignored. in addition, as word sized data is a requirement, the ls bit of the ea is ignored (and always clear). if bit-reversed addressing has already been enabled by setting the bren (xbrev<15>) bit, then a write to the xbrev register should not be immediately followed by an indirect read operation us ing the w register that has been designated as th e bit-reversed pointer. figure 4-2: bit-reversed address example note: the modulo corrected effective address is written back to the register only when pre- modify or post-modify addressing mode is used to compute the effective address. when an address offset (e.g., [w7+w2]) is used, modulo address correction is per- formed, but the contents of the register remains unchanged. note: all bit-reversed ea calculations assume word sized data (ls bit of every ea is always clear). the xb value is scaled accordingly to genera te compatible (byte) addresses. note: modulo addressing and bit-reversed addressing should not be enabled together. in the event that the user attempts to do this, bit reversed address- ing will assume priority when active for the x wagu, and x wagu modulo address- ing will be disabled. however, modulo addressing will continue to function in the x ragu. b3 b2 b1 0 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb = 0x0008 for a 16-word bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point
? 2005 microchip technology inc. preliminary ds70135c-page 39 DSPIC30F4011/4012 table 4-2: bit-reversed address sequence (16-entry) table 4-3: bit-reversed address modifier values for xbrev register normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 buffer size (words) xb<14:0> bit- reversed address modifier value* 32768 0x4000 16384 0x2000 8192 0x1000 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 *modifier values for buffer sizes greater than 1024 words will exceed the available data memory on the DSPIC30F4011/4012 devices.
DSPIC30F4011/4012 ds70135c-page 40 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 41 DSPIC30F4011/4012 5.0 interrupts the DSPIC30F4011/4012 has 30 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. the cpu is responsible fo r reading the interrupt vector table (ivt) and tran sferring the address con- tained in the interrupt vect or to the program counter. the interrupt vector is transferred from the program data bus into the program counter, via a 24-bit wide multiplexer on the input of the program counter. the interrupt vector table (ivt) and alternate inter- rupt vector table (aivt) are placed near the beginning of program memory (0x0 00004). the ivt and aivt are shown in figure 5-1. the interrupt controller is responsible for pre- processing the interrupts and processor exceptions, prior to their being presented to the processor core. the peripheral interrupts and traps are enabled, prioritized and controlled using centralized special function registers: ifs0<15:0>, ifs1<15:0>, ifs2<15:0> all interrupt request flags are maintained in these three registers. the flags are set by their respec- tive peripherals or extern al signals, and they are cleared via software. iec0<15:0>, iec1<15:0>, iec2<15:0> all interrupt enable contro l bits are maintained in these three registers. th ese control bits are used to individually enable interrupts from the peripherals or ex ternal signals. ipc0<15:0>... ipc11<7:0> the user assignable priority level associated with each of these interrupts is held centrally in these twelve registers. ipl<3:0> the current cpu pr iority level is explic- itly stored in the ipl bits. ipl<3> is present in the corcon register, whereas ipl<2:0> are present in the status register (s r) in the processor core. intcon1<15:0>, intcon2<15:0> global interrupt control functions are derived from these two registers. intcon1 contains the con- trol and status flags for the processor exceptions. the intcon2 register controls the external inter- rupt request signal behavior and the use of the alternate vector table. all interrupt sources can be user assigned to one of 7 priority levels, 1 through 7, via the ipcx registers. each interrupt source is associated with an interrupt vector, as shown in table 5-1. levels 7 and 1 repre- sent the highest and lowe st maskable priorities, respectively. if the nstdis bit (intco n1<15>) is set, nesting of interrupts is prevented. thus, if an interrupt is currently being serviced, processing of a new interrupt is pre- vented, even if the new interrupt is of higher priority than the one currently being serviced. certain interrupts have specialized control bits for fea- tures like edge or level trig gered interrupts, interrupt- on-change, etc. control of these features remains within the peripheral mo dule which generates the interrupt. the disi instruction can be used to disable the processing of interrupts of priorities 6 and lower for a certain number of instructions , during which the disi bit (intcon2<14>) remains set. when an interrupt is serviced, the pc is loaded with the address stored in the vector location in program mem- ory that corresponds to the interrupt. there are 63 dif- ferent vectors within the iv t (refer to figure 5-2). these vectors are contained in locations 0x000004 through 0x0000fe of program memory (refer to figure 5-2). these locations contain 24-bit addresses, and in order to preserve robustness, an address error trap will take place should the pc attemp t to fetch any of these words during normal execution. this prevents execu- tion of random data as a re sult of accidentally decre- menting a pc into vector space, accidentally mapping a data space address into vector space, or the pc roll- ing over to 0x000000 after reaching the end of imple- mented program memory space. execution of a goto instruction to this vector sp ace will also generate an address error trap. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). note: interrupt flag bits get set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit. user software should en sure the appropriate interrupt flag bits are clear prior to enabling an interrupt. note: assigning a priority level of 0 to an inter- rupt source is equiva lent to disabling that interrupt. note: the ipl bits become read-only whenever the nstdis bit has been set to ? 1 ?.
DSPIC30F4011/4012 ds70135c-page 42 preliminary ? 2005 microchip technology inc. 5.1 interrupt priority the user assignable interrupt priority (ip<2:0>) bits for each individual inte rrupt source are located in the ls 3- bits of each nibble, within the ipcx register(s). bit 3 of each nibble is not used and is read as a ? 0 ?. these bits define the priority level assig ned to a particular interrupt by the user. since more than one interrupt request source may be assigned to a specific user specified priority level, a means is provided to assign pr iority within a given level. this method is called ?nat ural order priority?. natural order priority is de termined by the position of an interrupt in the vector table, and only affects interrupt operation when mult iple interrupts with the same user-assigned priority become pending at the same time. table 5-1 lists the interr upt numbers and interrupt sources for the dspic devi ces and their associated vector numbers. the ability for the user to assign every interrupt to one of seven priority levels implies that the user can assign a very high overall priority level to an interrupt with a low natural order priority. for example, the plvd (low voltage detect) can be given a priority of 7. the int0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. table 5-1: interrupt vector table note: the user selectable priority levels start at 0, as the lowest priori ty, and level 7, as the highest priority. note 1: the natural order prio rity scheme has 0 as the highest priority and 53 as the lowest priority. 2: the natural order priority number is the same as the int number. int number vector number interrupt source highest natural order priority 0 8 int0 - external interrupt 0 1 9 ic1 - input capture 1 2 10 oc1 - output compare 1 3 11 t1 - timer 1 4 12 ic2 - input capture 2 5 13 oc2 - output compare 2 6 14 t2 - timer 2 7 15 t3 - timer 3 8 16 spi1 9 17 u1rx - uart1 receiver 10 18 u1tx - uart1 transmitter 11 19 adc - adc convert done 12 20 nvm - nvm write complete 13 21 si2c - i 2 c slave interrupt 14 22 mi2c - i 2 c master interrupt 15 23 input change interrupt 16 24 int1 - external interrupt 1 17 25 ic7 - input capture 7 18 26 ic8 - input capture 8 19 27 oc3 - output compare 3 20 28 oc4 - output compare 4 21 29 t4 - timer 4 22 30 t5 - timer 5 23 31 int2 - external interrupt 2 24 32 u2rx - uart2 receiver 25 33 u2tx - uart2 transmitter 26 34 reserved 27 35 c1 - combined irq for can1 28 36 reserved 29 37 reserved 30 38 reserved 31 39 reserved 32 40 reserved 33 41 reserved 34 42 reserved 35 43 reserved 36 44 reserved 37 45 reserved 38 46 reserved 39 47 pwm - pwm period match 40 48 qei - qei interrupt 41 49 reserved 42 50 reserved 43 51 flta - pwm fault a 44 52 reserved 45-53 53-61 reserved lowest natural order priority
? 2005 microchip technology inc. preliminary ds70135c-page 43 DSPIC30F4011/4012 5.2 reset sequence a reset is not a true except ion, because the interrupt controller is not involved in the reset process. the pro- cessor initializes its registers in response to a reset, which forces the pc to ze ro. the processor then begins program execution at location 0x000000. a goto instruction is stored in the first program memory loca- tion, immediately followed by the address target for the goto instruction. the processor executes the goto to the specified address and th en begins operation at the specified target (start) address. 5.2.1 reset sources there are 6 sources of erro r which will cause a device reset. watchdog time-out: the watchdog has timed out, indicating that the processor is no longer exec uting the correct flow of code. uninitialized w register trap: an attempt to use an unin itialized w register as an address pointer will cause a reset. illegal instruction trap: attempted execution of any unused opcodes will result in an illegal instruction trap. note that a fetch of an illegal instruct ion does not result in an illegal instruction trap if that instruction is flushed prior to execution due to a flow change. brown-out reset (bor): a momentary dip in th e power supply to the device has been detected , which may result in malfunction. trap lockout: occurrence of multiple trap conditions simulta- neously will cause a reset. 5.3 traps traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in figure 5-1. they are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. note that many of these trap conditions can only be detected when they occur. consequently, the question- able instruction is allowed to complete prior to trap exception processing. if the user chooses to recover from the error, the result of the erroneous action that caused the trap may have to be corrected. there are 8 fixed priority levels for traps: level 8 through level 15, which implies that the ipl3 is always set during processing of a trap. if the user is not currently ex ecuting a trap, and he sets the ipl<3:0> bits to a value of ? 0111 ? (level 7), then all interrupts are disabled, but traps can still be processed. 5.3.1 trap sources the following traps are prov ided with increasing prior- ity. however, since all traps can be nested, priority has little effect. math error trap: the math error trap executes under the following three circumstances: 1. should an attempt be made to divide by zero, the divide operation will be aborted on a cycle boundary and the trap taken. 2. if enabled, a math error trap will be taken when an arithmetic operation on either accumulator a or b causes an overflow from bit 31 and the accumulator guard bits are not utilized. 3. if enabled, a math error trap will be taken when an arithmetic operation on either accumulator a or b causes a catastrophic overflow from bit 39 and all saturation is disabled. 4. if the shift amount specified in a shift instruction is greater than the maximum allowed shift amount, a trap will occur. note: if the user does not intend to take correc- tive action in the event of a trap error condition, these vectors must be loaded with the address of a default handler that simply contains the reset instruction. if, on the other hand, one of the vectors containing an invalid address is called, an address error trap is generated.
DSPIC30F4011/4012 ds70135c-page 44 preliminary ? 2005 microchip technology inc. address error trap: this trap is initiated wh en any of the following circumstances occurs: 1. a misaligned data word access is attempted. 2. a data fetch from our unimplemented data memory location is attempted. 3. a data access of an unimplemented program memory location is attempted. 4. an instruction fetch from vector space is attempted. 5. execution of a ? bra #litera l? instruction or a ? goto #literal ? instruction, where literal is an unimplemented program memory address. 6. executing instructions after modifying the pc to point to unimplemented program memory addresses. the pc may be modified by loading a value into the stack and executing a return instruction. stack error trap: this trap is initiated under the following conditions: 1. the stack pointer is loaded with a value which is greater than the (user pr ogrammable) limit value written into the splim register (stack overflow). 2. the stack pointer is loaded with a value which is less than 0x0800 (simple stack underflow). oscillator fail trap: this trap is initiated if th e external oscillator fails and operation becomes reliant on an internal rc backup. 5.3.2 hard and soft traps it is possible that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). in such a case, the fixed priority shown in figure 5-2 is implemented, which may require the user to check if other traps are pending, in order to completely correct the fault. ?soft? traps include exceptions of priority level 8 through level 11, inclusive. the arithmetic error trap (level 11) falls into this category of traps. ?hard? traps include exceptions of priority level 12 through level 15, inclusive. the address error (level 12), stack error (level 13) an d oscillator error (level 14) traps fall into this category. each hard trap that occurs must be acknowledged before code execution of any type may continue. if a lower priority hard trap occurs while a higher priority trap is pending, acknowledged, or is being processed, a hard trap conflict will occur. the device is automatically reset in a hard trap conflict condition. the trapr status bit (rcon<15>) is set when the reset occurs, so that the condition may be detected in software. figure 5-1: trap vectors note: in the mac class of instructions, wherein the data space is split into x and y data space, unimplemented x space includes all of y space, and unimplemented y space includes all of x space. address error trap vector oscillator fail trap vector stack error trap vector reserved vector math error trap vector reserved oscillator fail trap vector address error trap vector reserved vector reserved vector interrupt 0 vector interrupt 1 vector ? ? ? interrupt 52 vector interrupt 53 vector math error trap vector decreasing priority 0x000000 0x000014 reserved stack error trap vector reserved vector reserved vector interrupt 0 vector interrupt 1 vector ? ? ? interrupt 52 vector interrupt 53 vector ivt aivt 0x000080 0x00007e 0x0000fe reserved 0x000094 reset - goto instruction reset - goto address 0x000002 reserved 0x000082 0x000084 0x000004 reserved vector
? 2005 microchip technology inc. preliminary ds70135c-page 45 DSPIC30F4011/4012 5.4 interrupt sequence all interrupt event flags are sampled in the beginning of each instruction cycle by t he ifsx registers. a pending interrupt request (irq) is indicated by the flag bit being equal to a ? 1 ? in an ifsx register . the irq will cause an interrupt to occur if the corr esponding bit in the interrupt enable (iecx) register is se t. for the rema inder of the instruction cycle, the prioriti es of all pending interrupt requests are evaluated. if there is a pending irq with a priority level greater than the current processor prio rity level in the ipl bits, the processor will be interrupted. the processor then stacks the current program counter and the low byte of the proc essor status register (srl), as shown in figure 5-2. the low byte of the status reg- ister contains the processor priority level at the time, prior to the beginning of th e interrupt cycle. the proces- sor then loads the priority leve l for this interrupt into the status register. this action will disable all lower priority interrupts until the completi on of the interrupt service routine. figure 5-2: interrupt stack frame the retfie (return from interrupt) instruction will unstack the program counter and status registers to return the processor to its state prior to the interrupt sequence. 5.5 alternate vector table in program memory, the interrupt vector table (ivt) is followed by the alternate interrupt vector table (aivt), as shown in figure 5-1. acce ss to the alternate vector table is provided by the al tivt bit in the intcon2 register. if the altivt bit is set, all interrupt and excep- tion processes will use the alternate vectors instead of the default vectors. the alternate vectors are organized in the same manner as t he default vectors. the aivt supports emulation and debug ging efforts by providing a means to switch between an application and a sup- port environment, without requiring the interrupt vec- tors to be reprogrammed. this feature also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not required, the program memory allo- cated to the aivt may be used for other purposes. aivt is not a protected section and may be freely programmed by the user. 5.6 fast context saving a context saving option is available using shadow reg- isters. shadow registers are provided for the dc, n, ov, z and c bits in sr, and the registers w0 through w3. the shadows are only on e level deep. the shadow registers are accessible using the push.s and pop.s instructions only. when the processor vector s to an interrupt, the push.s instruction can be used to store the current value of the aforementio ned registers into their respective shadow registers. if an isr of a certain priority uses the push.s and pop.s instructions for fast context saving, then a higher priority isr should no t include the same instruc- tions. users must save the key registers in software during a lower priority interrup t, if the higher priority isr uses fast context saving. 5.7 external interrupt requests the interrupt controller suppo rts five external interrupt request signals, int0-int4. these inputs are edge sensitive; they require a lo w-to-high or a high-to-low transition to generate an interrupt request. the intcon2 register has five bits, int0ep-int4ep, that select the polarity of the edge detection circuitry. 5.8 wake-up from sleep and idle the interrupt controller may be used to wake up the processor from either sleep or idle modes, if sleep or idle mode is active when th e interrupt is generated. if an enabled interrupt request of sufficient priority is received by the interrupt co ntroller, then the standard interrupt request is presented to the processor. at the same time, the processor will wake-up from sleep or idle and begin execution of the interrupt service routine (isr) needed to proc ess the interrupt request. note 1: the user can always lower the priority level by writing a new value into sr. the interrupt service routine must clear the interrupt flag bits in the ifsx regis ter before lowering the processor interrupt prio rity, in order to avoid recursive interrupts. 2: the ipl3 bit (corcon<3>) is always clear when interrupts are being processed. it is set only during execution of traps. 0 15 w15 (before call ) w15 (after call ) stack grows towards higher address push : [w15++] pop : [--w15] 0x0000 pc<15:0> srl ipl3 pc<22:16>
DSPIC30F4011/4012 ds70135c-page 46 preliminary ? 2005 microchip technology inc. table 5-2: interrupt controller register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name adr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state intcon1 0080 nstdis ? ? ? ? ovate ovbte covte ? ? ? matherr addrerr stkerr oscfail ? 0000 0000 0000 0000 intcon2 0082 altivt ? ? ? ? ? ? ? ? ? ? ? ? int2ep int1ep int0ep 0000 0000 0000 0000 ifs0 0084 cnif mi2cif si2cif nvmif adif u1txif u1rxi f spi1if t3if t2if oc2if ic2if t1if oc1if ic1if int0if 0000 0000 0000 0000 ifs1 0086 ? ? ? ? c1if ? u2txif u2rxif int2if t5if t4if oc4if oc3if ic8if ic7if int1if 0000 0000 0000 0000 ifs2 0088 ? ? ? ? fltaif ? ? qeiif pwmif ? ? ? ? ? ? ? 0000 0000 0000 0000 iec0 008c cnie mi2cie si2cie nvmie adie u1txie u1r xie spi1ie t3ie t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie 0000 0000 0000 0000 iec1 008e ? ? ? ? c1ie ? u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie ic8ie ic7ie int1ie 0000 0000 0000 0000 iec2 0090 ? ? ? ? fltaie ? ? qeiie pwmie ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc0 0094 ? t1ip<2:0> ? oc1ip<2:0> ? ic1ip<2:0> ? int0ip<2:0> 0100 0100 0100 0100 ipc1 0096 ? t31p<2:0> ? t2ip<2:0> ? oc2ip<2:0> ? ic2ip<2:0> 0100 0100 0100 0100 ipc2 0098 ? adip<2:0> ? u1txip<2:0> ? u1rxip<2:0> ? spi1ip<2:0> 0100 0100 0100 0100 ipc3 009a ? cnip<2:0> ? mi2cip<2:0> ? si2cip<2:0> ? nvmip<2:0> 0100 0100 0100 0100 ipc4 009c ? oc3ip<2:0> ? ic8ip<2:0> ? ic7ip<2:0> ? int1ip<2:0> 0100 0100 0100 0100 ipc5 009e ? int2ip<2:0> ? t5ip<2:0> ? t4ip<2:0> ? oc4ip<2:0> 0100 0100 0100 0100 ipc6 00a0 ? c1ip<2:0> ? ? ? ? ? u2txip<2:0> ? u2rxip<2:0> 0100 0000 0100 0100 ipc7 00a2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc8 00a4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc9 00a6 ? pwmip<2:0> ? ? ? ? ? ? ? ? ? ? ? ? 0100 0000 0100 0100 ipc10 00a8 ? fltaip<2:0> ? ? ? ? ? ? ? ? ? qeiip<2:0> 0100 0000 0000 0100 ipc11 00aa ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 47 DSPIC30F4011/4012 6.0 flash program memory the dspic30f family of devices contains internal program flash memory for executing user code. there are two methods by which the user can program this memory: 1. in-circuit serial programming? (icsp?) 2. run time self-programming (rtsp) 6.1 in-circuit serial programming (icsp) dspic30f devices can be serially programmed while in the end application circuit. this is simply done with two lines for programming clock and programming data (which are named pgc and pgd respectively), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows cu stomers to manu- facture boards with unpr ogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 6.2 run time self-programming (rtsp) rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user may erase program memory, 32 instructions (96 bytes) at a time and can write program memory data, 32 instructions (96 bytes) at a time. 6.3 table instruction operation summary the tblrdl and the tblwtl instructions are used to read or write to bits <15:0> of program memory. tblrdl and tblwtl can access program memory in word or byte mode. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can access program memory in word or byte mode. a 24-bit program memory address is formed using bits<7:0> of the tblpag register and the effective address (ea) from a w regist er specified in the table instruction, as shown in figure 6-1. figure 6-1: addressing for table and nvm registers note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). 0 program counter 24 bits nvmadru reg 8 bits 16 bits program using tblpag reg 8 bits working reg ea 16 bits using byte 24-bit ea 1/0 0 1/0 select ta b l e instruction nvmadr addressing counter using nvmadr reg ea user/configuration space select
DSPIC30F4011/4012 ds70135c-page 48 preliminary ? 2005 microchip technology inc. 6.4 rtsp operation the dspic30f flash program memory is organized into rows and panels. each row consists of 32 instruc- tions, or 96 bytes. each pa nel consists of 128 rows, or 4k x 24 instructions. rtsp al lows the user to erase one row (32 instructions) at a time and to program 32 instructions at one time. each panel of program memory contains write latches that hold 32 instructions of programming data. prior to the actual programming oper ation, the write data must be loaded into the panel wr ite latches. the data to be programmed into the panel is loaded in sequential order into the write latches; instruction 0 , instruction 1 , etc. the addresses loaded must always be from an even group of 32 boundary. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the write latches. programming is performed by setting the special bits in the nvmcon register. 32 tblwtl and 32 tblwth instructions are required to load the 32 instructions. all of the table write operat ions are single word writes (2 instruction cycles), because only the table latches are written. after the latches are written, a programming operation needs to be initiated to program the data. the flash program memory is readable, writable and erasable during normal operation over the entire v dd range. 6.5 rtsp control registers the four sfrs used to read and write the program flash memory are: nvmcon nvmadr nvmadru nvmkey 6.5.1 nvmcon register the nvmcon register contro ls which blocks are to be erased, which memory type is to be programmed, and start of the programming cycle. 6.5.2 nvmadr register the nvmadr register is used to hold the lower two bytes of the effective address. the nvmadr register captures the ea<15:0> of the last table instruction that has been executed and selects the row to write. 6.5.3 nvmadru register the nvmadru register is used to hold the upper byte of the effective address. the nvmadru register cap- tures the ea<23:16> of the last table instruction that has been executed. 6.5.4 nvmkey register nvmkey is a write-only regist er that is used for write protection. to start a programming or an erase sequence, the user must consecutively write 0x55 and 0xaa to the nvmkey register . refer to section 6.6 for further details. note: the user can also directly write to the nvmadr and nvmadru registers to specify a program memory address for erasing or programming.
? 2005 microchip technology inc. preliminary ds70135c-page 49 DSPIC30F4011/4012 6.6 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. a programming operation is nominally 2 msec in duration and the processor st alls (waits) until the oper- ation is finished. setting the wr bit (nvmcon<15>) starts the operation, and the wr bit is automatically cleared when the oper ation is finished. 6.6.1 programming algorithm for program flash the user can erase or program one row of program flash memory at a time. the general process is: 1. read one row of program flash (32 instruction words) and store into data ram as a data ?image?. 2. update the data image with the desired new data. 3. erase program flash row. a) setup nvmcon register for multi-word, program flash, erase, and set wren bit. b) write address of row to be erased into nvmadru/nvmdr. c) write ?55? to nvmkey. d) write ?aa? to nvmkey. e) set the wr bit. this will begin erase cycle. f) cpu will stall for the duration of the erase cycle. g) the wr bit is clear ed when erase cycle ends. 4. write 32 instruction words of data from data ram ?image? into the program flash write latches. 5. program 32 instruction words into program flash. a) setup nvmcon register for multi-word, program flash, program, and set wren bit. b) write ?55? to nvmkey. c) write ?aa? to nvmkey. d) set the wr bit. this will begin program cycle. e) cpu will stall for duration of the program cycle. f) the wr bit is cleared by the hardware when program cycle ends. 6. repeat steps 1 through 5 as needed to program desired amount of pr ogram flash memory. 6.6.2 erasing a row of program memory example 6-1 shows a code sequence that can be used to erase a row (32 instruct ions) of program memory. example 6-1: erasing a row of program memory ; setup nvmcon for erase operation, multi word write ; program memory selec ted, and writes enabled mov #0x4041,w0 ; mov w0 , nvmcon ; init nvmcon sfr ; init pointer to row to be erased mov #tblpage(prog_addr),w0 ; mov w0 , nvmadru ; initialize pm page boundary sfr mov #tbloffset(prog_addr),w0 ; i ntialize in-page ea[15:0] pointer mov w0, nvmadr ; intialize nvmadr sfr disi #5 ; block all inte rrupts with priority <7 ; for next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted
DSPIC30F4011/4012 ds70135c-page 50 preliminary ? 2005 microchip technology inc. 6.6.3 loading write latches example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 tblwtl and 32 tblwth instructions are needed to load the write latches select ed by the table pointer. example 6-2: loading write latches 6.6.4 initiating the programming sequence for protection, the write in itiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the pr ogramming command has been executed, the user must wa it for the programming time until programming is comp lete. the two instructions following the start of the programming sequence should be nop s. example 6-3: initiating a programming sequence ; set up a pointer to the first program memory locat ion to be written ; program memory selec ted, and writes enabled mov #0x0000,w0 ; mov w0 , tblpag ; initialize pm page boundary sfr mov #0x6000,w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0,w2 ; mov #high_byte_0,w3 ; tblwtl w2 , [w0] ; write pm low wor d into program latch tblwth w3 , [w0++] ; write pm high by te into program latch ; 1st_program_word mov #low_word_1,w2 ; mov #high_byte_1,w3 ; tblwtl w2 , [w0] ; write pm low wor d into program latch tblwth w3 , [w0++] ; write pm high by te into program latch ; 2nd_program_word mov #low_word_2,w2 ; mov #high_byte_2,w3 ; tblwtl w2 , [w0] ; write pm low wor d into program latch tblwth w3 , [w0++] ; write pm high by te into program latch ; 31st_program_word mov #low_word_31,w2 ; mov #high_byte_31,w3 ; tblwtl w2 , [w0] ; write pm low wor d into program latch tblwth w3 , [w0++] ; write pm high by te into program latch note: in example 6-2, the contents of th e upper byte of w3 has no effect. disi #5 ; block all i nterrupts with priority <7 ; for next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted
? 2005 microchip technology inc. preliminary ds70135c-page 51 DSPIC30F4011/4012 table 6-1: nvm register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr ? ? ? ? twri ? progop<6:0> 0000 0000 0000 0000 nvmadr 0762 nvmadr<15:0> uuuu uuuu uuuu uuuu nvmadru 0764 ? ? ? ? ? ? ? ? ? nvmadr<22:16> 0000 0000 uuuu uuuu nvmkey 0766 ? ? ? ? ? ? ? ? key<7:0> 0000 0000 0000 0000 legend: u = uninitialized bit
DSPIC30F4011/4012 ds70135c-page 52 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 53 DSPIC30F4011/4012 7.0 data eeprom memory the data eeprom memory is readable and writable during normal operation over the entire v dd range. the data eeprom memory is directly mapped in the program memory address space. the four sfrs used to read and write the program flash memory are used to access data eeprom memory, as well. as descri bed in section 4.0, these registers are: nvmcon nvmadr nvmadru nvmkey the eeprom data memory allows read and write of single words and 16-word bl ocks. when interfacing to data memory, nvmadr, in conjunction with the nvmadru register, is used to address the eeprom location being accessed. tblrdl and tblwtl instruc- tions are used to read and write data eeprom. the DSPIC30F4011/4012 device has 1 kbyte (512 words) of data eeprom, with an address range from 0x7ffc00 to 0x7ffffe. a word write operation should be preceded by an erase of the corresponding memory location(s). the write typically requires 2 ms to complete, but the write time will vary with volt age and temperature. a program or erase oper ation on the data eeprom does not stop the instruction flow. th e user is respon- sible for waiting for the app ropriate duration of time before initiating another data eeprom write/erase operation. attempting to re ad the data eeprom while a programming or erase operat ion is in progress results in unspecified data. control bit wr initiates writ e operations, similar to pro- gram flash writes. this bit cannot be cleared, only set, in software. this bit is clea red in hardware at the com- pletion of the write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset, or a wdt time-out reset, during normal oper- ation. in these situations, following reset, the user can check the wrerr bit and re write the location. the address register nvma dr remains unchanged. 7.1 reading the data eeprom a tblrd instruction reads a word at the current pro- gram word address. this example uses w0 as a pointer to data eeprom. the result is placed in register w4, as shown in example 7-1. example 7-1: data eeprom read note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). note: interrupt flag bit nvmif in the ifs0 regis- ter is set when write is complete. it must be cleared in software. mov #low_addr_word,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag tblrdl [ w0 ], w4 ; read data eeprom
DSPIC30F4011/4012 ds70135c-page 54 preliminary ? 2005 microchip technology inc. 7.2 erasing data eeprom 7.2.1 erasing a block of data eeprom in order to erase a block of data eeprom, the nvmadru and nvmadr registers must initially point to the block of memory to be erased. configure nvmcon for erasing a block of data eeprom, and set the erase and wren bits in nvmcon register. setting the wr bit initiates the erase, as shown in example 7-2. example 7-2: data eeprom block erase 7.2.2 erasing a word of data eeprom the tblpag and nvmadr registers must point to the block. select erase a block of data flash, and set the erase and wren bits in nvmcon register. set- ting the wr bit initiate s the erase, as shown in example 7-3. example 7-3: data eeprom word erase ; select data eeprom blo ck, erase, wren bits mov #0x4045,w0 mov w0 , nvmcon ; initialize nvmcon sfr ; start erase cycle by setting wr after writing key sequence disi #5 ; block all interru pts with priority <7 ; for next 5 instructions mov #0x55,w0 ; mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; initiate erase sequence nop nop ; erase cycle will complete in 2ms. cpu is not stalled for the data erase cycle ; user can poll wr bi t, use nvmif or timer irq to determine erasure complete ; select data eeprom word, erase, wren bits mov #0x4044,w0 mov w0 , nvmcon ; start erase cycle by setting wr after writing key sequence disi #5 ; block all in terrupts with priority <7 ; for next 5 instructions mov #0x55,w0 ; mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; writ e the 0xaa key bset nvmcon,#wr ; init iate erase sequence nop nop ; erase cycle will complete in 2ms. cpu is not stalled for the da ta erase cycle ; user can poll wr bit, us e nvmif or timer irq to determine er asure complete
? 2005 microchip technology inc. preliminary ds70135c-page 55 DSPIC30F4011/4012 7.3 writing to the data eeprom to write an eeprom data location, the following sequence must be followed: 1. erase data eeprom word. a) select word, data eeprom, erase and set wren bit in nvmcon register. b) write address of word to be erased into nvmadru/nvmadr. c) enable nvm interrupt (optional). d) write ?55? to nvmkey. e) write ?aa? to nvmkey. f) set the wr bit. this will begin erase cycle. g) either poll nvmif bi t or wait for nvmif interrupt. h) the wr bit is cleared when the erase cycle ends. 2. write data word into data eeprom write latches. 3. program 1 data word into data eeprom. a) select word, data eeprom, program, and set wren bit in nvmcon register. b) enable nvm write done interrupt (optional). c) write ?55? to nvmkey. d) write ?aa? to nvmkey. e) set the wr bit. this will begin program cycle. f) either poll nvmif bit or wait for nvm interrupt. g) the wr bit is cleared when the write cycle ends. the write will not initiate if the above sequence is not exactly followed (write 0x55 to nvmkey, write 0xaa to nvmcon, then set wr bit) fo r each word. it is strongly recommended that interrupt s be disabled during this code segment. additionally, the wren bit in nvmcon must be set to enable writes. this mechanism prevents accidental writes to data eeprom, due to unexpected code exe- cution. the wren bit should be kept clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequen ce has been initiated, clearing the wren bit will not affect the current write cycle. the wr bit will be inhibited from bei ng set unless the wren bit is set. the wren bit must be set on a previous instruc- tion. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the non-volatile memory write complete interrupt fl ag bit (nvmif) is set. the user may either enable this interrupt, or poll this bit. nvmif must be cleared by software. 7.3.1 writing a word of data eeprom once the user has erased t he word to be programmed, then a table write instruction is used to write one write latch, as shown in example 7-4. example 7-4: data eeprom word write ; point to data memory mov #low_addr_word,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag mov #low(word),w2 ; get data tblwtl w2 , [ w0] ; write data ; the nvmadr captures last table access address ; select data eepro m for 1 word op mov #0x4004,w0 mov w0 , nvmcon ; operate key to allow write operation disi #5 ; block all i nterrupts with priority <7 ; for next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; in itiate program sequence nop nop ; write cycle will complete in 2ms. cpu is not stall ed for the data write cycle ; user can poll wr bit, u se nvmif or timer irq to determine write complete
DSPIC30F4011/4012 ds70135c-page 56 preliminary ? 2005 microchip technology inc. 7.3.2 writing a block of data eeprom to write a block of data e eprom, write to all sixteen latches first, then set the nvmcon register and program the block. example 7-5: data eeprom block write 7.4 write verify depending on the applica tion, good programming practice may dictate that th e value written to the mem- ory should be verified agains t the original value. this should be used in applicati ons where excessive writes can stress bits near the specification limit. 7.5 protection against spurious write there are conditions when the device may not want to write to the data eeprom me mory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared; also, the power-up timer prevents eeprom write. the write initiate sequence and the wren bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. mov #low_addr_wo rd,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag mov #data1,w2 ; get 1st data tblwtl w2 , [ w0]++ ; write data mov #data2,w2 ; get 2nd data tblwtl w2 , [ w0]++ ; write data mov #data3,w2 ; get 3rd data tblwtl w2 , [ w0]++ ; write data mov #data4,w2 ; get 4th data tblwtl w2 , [ w0]++ ; write data mov #data5,w2 ; get 5th data tblwtl w2 , [ w0]++ ; write data mov #data6,w2 ; get 6th data tblwtl w2 , [ w0]++ ; write data mov #data7,w2 ; get 7th data tblwtl w2 , [ w0]++ ; write data mov #data8,w2 ; get 8th data tblwtl w2 , [ w0]++ ; write data mov #data9,w2 ; get 9th data tblwtl w2 , [ w0]++ ; write data mov #data10,w2 ; get 10th data tblwtl w2 , [ w0]++ ; write data mov #data11,w2 ; get 11th data tblwtl w2 , [ w0]++ ; write data mov #data12,w2 ; get 12th data tblwtl w2 , [ w0]++ ; write data mov #data13,w2 ; get 13th data tblwtl w2 , [ w0]++ ; write data mov #data14,w2 ; get 14th data tblwtl w2 , [ w0]++ ; write data mov #data15,w2 ; get 15th data tblwtl w2 , [ w0]++ ; write data mov #data16,w2 ; get 16th data tblwtl w2 , [ w0]++ ; write data. the nvmadr captures last ta ble access address. mov #0x400a,w0 ; select data eeprom for multi word op mov w0 , nvmcon ; operate key to allow program operation disi #5 ; block all int errupts with priority <7 ; for next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start write cycle nop nop
? 2005 microchip technology inc. preliminary ds70135c-page 57 DSPIC30F4011/4012 8.0 i/o ports all of the device pins (except v dd , v ss , mclr and osc1/clkin) are shared bet ween the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 8.1 parallel i/o (pio) ports when a peripheral is enabl ed and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pi n is disabled. the i/o pin may be read, but the output driver for the parallel port bit will be disabled. if a peri pheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. all port pins have three registers directly associated with the operation of the po rt pin. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx), read the latch. writes to the latch, write the latch (latx). reads from the port (portx), read the po rt pins, and writes to the port pins, write the latch (latx). any bit and its associated data and control registers that are not valid for a particular device will be disabled. that means the corresponding latx and trisx registers and the port pin will read as zeros. when a pin is shared with an other peripheral or func- tion that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. an example is the int4 pin. the format of the registers for portx are shown in ta b l e 8 - 1 . the trisx (data direction control) register controls the direction of the pins. the latx register supplies data to the outputs, and is readable/writable. reading the portx register yields the state of the input pins, while writing the portx register modifies the contents of the latx register. a parallel i/o (pio) port that shares a pin with a periph- eral is, in general, subservie nt to the peripheral. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pad cell. figure 8-2 shows how ports are shared with other peripherals, and the associated i/o cell (pad) to which they are connected. table 8-1 and shows the formats of the registers for the shared ports, portb through portg. figure 8-1: block diagram of a dedicated port structure note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). q d ck wr lat + tris latch i/o pad wr port data bus q d ck data latch read lat read port read tris wr tris i/o cell dedicated port module
DSPIC30F4011/4012 ds70135c-page 58 preliminary ? 2005 microchip technology inc. figure 8-2: block diagram of a shared port structure 8.2 configuring analog port pins the use of the adpcfg and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs mu st have their correspond- ing tris bit set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. when reading the port register, all pins configured as analog input channel will read as cleared (a low level). pins configured as digital inputs will not convert an ana- log input. analog levels on any pin that is defined as a digital input (including the anx pins), may cause the input buffer to consume current that exceeds the device specifications. 8.2.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be a nop. example 8-1: port write/read example q d ck wr lat + tris latch i/o pad wr port data bus q d ck data latch read lat read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o cell peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable mov 0xff00, w0 ; confi gure portb<15:8> ; as inputs mov w0, trisbb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction
? 2005 microchip technology inc. preliminary ds70135c-page 59 DSPIC30F4011/4012 table 8-1: DSPIC30F4011 port register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisb 02c6 ? ? ? ? ? ? ? trisb8 trisb7 trisb6 trisb5 trisb 4 trisb3 trisb2 trisb1 trisb0 0000 0001 1111 1111 portb 02c8 ? ? ? ? ? ? ? rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 0000 0000 0000 0000 latb 02cb ? ? ? ? ? ? ? latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 0000 0000 0000 0000 trisc 02cc trisc15 trisc14 trisc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 1110 0000 0000 0000 portc 02ce rc15 rc14 rc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 latc 02d0 latc15 latc14 latc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 trisd 02d2 ? ? ? ? ? ? ? ? ? ? ? ? trisd3 trisd2 trisd1 trisd0 0000 0000 0000 1111 portd 02d4 ? ? ? ? ? ? ? ? ? ? ? ? rd3 rd2 rd1 rd0 0000 0000 0000 0000 latd 02d6 ? ? ? ? ? ? ? ? ? ? ? ? latd3 latd2 latd1 latd0 0000 0000 0000 0000 trise 02d8 ? ? ? ? ? ? ? trise8 ? ? trise5 trise4 trise3 t rise2 trise1 trise0 0000 0001 0011 1111 porte 02da ? ? ? ? ? ? ? re8 ? ? re5 re4 re3 re2 re1 re0 0000 0000 0000 0000 late 02dc ? ? ? ? ? ? ? late8 ? ? late5 late4 late3 late2 late1 late0 0000 0000 0000 0000 trisf 02ee ? ? ? ? ? ? ? ? ? trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 0000 0000 0111 1111 portf 02e0 ? ? ? ? ? ? ? ? ? rf6 rf5 rf4 rf3 rf2 rf1 rf0 0000 0000 0000 0000 latf 02e2 ? ? ? ? ? ? ? ? ? latf6 latf5 latf4 latf3 latf2 latf1 latf0 0000 0000 0000 0000 legend: u = uninitialized bit
DSPIC30F4011/4012 ds70135c-page 60 preliminary ? 2005 microchip technology inc. table 8-2: dspic30f4012 port register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisb 02c6 ? ? ? ? ? ? ? ? ? ? trisb5 trisb4 trisb3 t risb2 trisb1 trisb0 0000 0000 0011 1111 portb 02c8 ? ? ? ? ? ? ? ? ? ? rb5 rb4 rb3 rb2 rb1 rb0 0000 0000 0000 0000 latb 02cb ? ? ? ? ? ? ? ? ? ? latb5 latb4 latb3 latb2 latb1 latb0 0000 0000 0000 0000 trisc 02cc trisc15 trisc14 trisc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 1110 0000 0000 0000 portc 02ce rc15 rc14 rc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 latc 02d0 latc15 latc14 latc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 trisd 02d2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? trisd1 trisd0 0000 0000 0000 0011 portd 02d4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? rd1 rd0 0000 0000 0000 0000 latd 02d6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? latd1 latd0 0000 0000 0000 0000 trise 02d8 ? ? ? ? ? ? ? trise8 ? ? trise5 trise4 trise3 t rise2 trise1 trise0 0000 0001 0011 1111 porte 02da ? ? ? ? ? ? ? re8 ? ? re5 re4 re3 re2 re1 re0 0000 0000 0000 0000 late 02dc ? ? ? ? ? ? ? late8 ? ? late5 late4 late3 late2 late1 late0 0000 0000 0000 0000 trisf 02ee ? ? ? ? ? ? ? ? ? ? ? ? trisf3 trisf2 ? ? 0000 0000 0000 1100 portf 02e0 ? ? ? ? ? ? ? ? ? ? ? ? rf3 rf2 ? ? 0000 0000 0000 0000 latf 02e2 ? ? ? ? ? ? ? ? ? ? ? ? latf3 latf2 ? ? 0000 0000 0000 0000 legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 61 DSPIC30F4011/4012 8.3 input change notification module the input change notificati on module provides the dspic30f devices the ability to generate interrupt requests to the processor in response to a change-of- state on selected input pins . this module is capable of detecting input change-of-st ates even in sleep mode, when the clocks are disabled . there are 10 external signals (cn0 through cn7, cn17 and cn18) that may be selected (enabled) fo r generating an interrupt request on a change-of-state. please refer to the pin diagrams for cn pin locations. table 8-3: input change notification register map (bits 7-0) note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state cnen1 00c0 cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 0000 0000 0000 cnen2 00c2 ? ? ? ? ? cn18ie* cn17ie* ? 0000 0000 0000 0000 cnpu1 00c4 cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 0000 0000 0000 cnpu2 00c6 ? ? ? ? ? cn18pue* cn17pue* ? 0000 0000 0000 0000 legend: u = uninitialized bit *not available on dspic30f4012
DSPIC30F4011/4012 ds70135c-page 62 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 63 DSPIC30F4011/4012 9.0 timer1 module this section describes th e 16-bit general purpose (gp) timer1 module and associated operational modes. figure 9-1 depicts t he simplified block diagram of the 16-bit timer1 module. the following sections prov ide a detailed description, including setup and control re gisters along with associ- ated block diagrams for the operational modes of the timers. the timer1 module is a 16-bit timer which can serve as the time counter for the real-time clock, or operate as a free running interval timer/ counter. the 16-bit timer has the following modes: 16-bit timer 16-bit synchronous counter 16-bit asynchronous counter further, the following operational characteristics are supported: timer gate operation selectable prescaler settings timer operation during cpu idle and sleep modes interrupt on 16-bit period register match or falling edge of external gate signal these operating modes are de termined by setting the appropriate bit(s) in the 16 -bit sfr, t1con. figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit timer mode: in the 16-bit timer mode, the timer increments on every instruction cycle up to a match value, preloaded into the period register pr1, then resets to 0 and co ntinues to count. when the cpu goes into the idle mode, the timer will stop incrementing, unless the tsidl (t1con<13>) bit = 0 . if tsidl = 1 , the timer module logic will resume the incrementing sequence upon termination of the cpu idle mode. 16-bit synchronous counter mode: in the 16-bit synchronous counter mode, the timer increments on the rising edge of the appl ied external clock signal, which is synchronized with the internal phase clocks. the timer counts up to a ma tch value preloaded in pr1, then resets to 0 and continues. when the cpu goes into the idle mode, the timer will stop incrementing, unless the respective tsidl bit = 0 . if tsidl = 1 , the timer module logic will resume the incrementing sequence upon termination of the cpu idle mode. 16-bit asynchronous counter mode: in the 16-bit asynchronous counter mode, the timer increments on every rising edge of the a pplied external clock signal. the timer counts up to a ma tch value preloaded in pr1, then resets to 0 and continues. when the timer is configured for the asynchronous mode of operation and the cpu goes into the idle mode, the timer will stop incrementing if tsidl = 1 . note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: timer1 is a ?type a? timer. please refer to the specifications for a type a timer in section 24.0 electrical characteristics of this document.
DSPIC30F4011/4012 ds70135c-page 64 preliminary ? 2005 microchip technology inc. figure 9-1: 16-bit timer1 mo dule block diagram (type a timer) 9.1 timer gate operation the 16-bit timer can be plac ed in the gated time accu- mulation mode. this mode allows the internal t cy to increment the respective time r when the gate input sig- nal (t1ck pin) is asserted high. control bit tgate (t1con<6>) must be set to enable this mode. the timer must be enabled (ton = 1 ) and the timer clock source set to internal (tcs = 0 ). when the cpu goes into the idle mode, the timer will stop incrementing, unless tsidl = 0 . if tsidl = 1 , the timer will resume the incrementing sequence upon termination of the cpu idle mode. 9.2 timer prescaler the input clock (f osc /4 or external clock) to the 16-bit timer, has a prescale option of 1:1, 1:8, 1:64, and 1:256 selected by control bits tckps<1:0> (t1con<5:4>). the prescaler counter is cleared when any of the following occurs: a write to the tmr1 register clearing of the ton bit (t1con<15>) device reset such as por and bor however, if the time r is disabled (ton = 0 ), then the timer prescaler cannot be reset since the prescaler clock is halted. tmr1 is not cleared when t1con is written. it is cleared by writing to the tmr1 register. 9.3 timer operation during sleep mode during cpu sleep mode, t he timer will operate if: the timer module is enabled (ton = 1 ) and the timer clock source is selected as external (tcs = 1 ) and the tsync bit (t1con<2>) is asserted to a logic 0, which defines the exte rnal clock source as asynchronous when all three conditions ar e true, the timer will con- tinue to count up to the peri od register and be reset to 0x0000. when a match between the timer and the period regis- ter occurs, an interrupt can be generated, if the respective timer interrupt enable bit is asserted. ton sync sosci sosco/ pr1 t1if equal comparator x 16 tmr1 reset lposcen event flag 1 0 tsync q q d ck tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs 1 x 0 1 tgate 0 0 (3) gate sync
? 2005 microchip technology inc. preliminary ds70135c-page 65 DSPIC30F4011/4012 9.4 timer interrupt the 16-bit timer has the abilit y to generate an interrupt on period match. when the timer count matches the period register, the t1if bit is asserted and an interrupt will be generated, if enabl ed. the t1if bit must be cleared in software. the timer interrupt flag t1if is located in the ifs0 control register in the interrupt controller. when the gated time accumu lation mode is enabled, an interrupt will also be generated on the falling edge of the gate signal (at the end of the accumulation cycle). enabling an interrupt is ac complished via the respec- tive timer interrupt enable bit, t1ie. the timer inter- rupt enable bit is located in the iec0 control register in the interrupt controller. 9.5 real-time clock timer1, when operating in real-time clock (rtc) mode, provides time-of-da y and event time stamping capabilities. key operational features of the rtc are: operation from 32 khz lp oscillator 8-bit prescaler low power real-time clock interrupts these operating modes are determined by setting the appropriate bit(s) in the t1con control register figure 9-2: recommended components for timer1 lp oscillator rtc 9.5.1 rtc oscillator operation when the ton = 1 , tcs = 1 and tgate = 0 , the timer increments on the rising edge of the 32 khz lp oscilla- tor output signal, up to the va lue specified in the period register, and is then reset to ? 0 ?. the tsync bit must be asserted to a logic ? 0 ? (asynchronous mode) fo r correct operation. enabling lposcen (osccon<1>) will disable the normal timer and counter modes and enable a timer carry-out wake-up event. when the cpu enters sleep mode, the rtc will con- tinue to operate, provided t he 32 khz external crystal oscillator is active and the control bits have not been changed. the tsidl bit s hould be cleared to ? 0 ? in order for rtc to continue operation in idle mode. 9.5.2 rtc interrupts when an interrupt event occurs, the respective inter- rupt flag, t1if, is asserted an d an interrupt will be gen- erated, if enabled. the t1 if bit must be cleared in software. the respective ti mer interrupt flag, t1if, is located in the ifs0 status register in the interrupt controller. enabling an interrupt is ac complished via the respec- tive timer interrupt enable bit, t1ie. the timer inter- rupt enable bit is located in the iec0 control register in the interrupt controller. sosci sosco r c1 c2 dspic30fxxxx 32.768 khz xtal c1 = c2 = 18 pf; r = 100k
DSPIC30F4011/4012 ds70135c-page 66 preliminary ? 2005 microchip technology inc. table 9-1: timer1 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state tmr1 0100 timer 1 register uuuu uuuu uuuu uuuu pr1 0102 period register 1 1111 1111 1111 1111 t1con 0104 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? tsync tcs ? 0000 0000 0000 0000 legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 67 DSPIC30F4011/4012 10.0 timer2/3 module this section describes th e 32-bit general purpose (gp) timer module (timer2/3) and associated opera- tional modes. figure 10-1 de picts the simplified block diagram of the 32-bit ti mer2/3 module. figure 10-2 and figure 10-3 show timer2/3 configured as two independent 16-bit time rs; timer2 and timer3, respectively. the timer2/3 module is a 32-bit timer, which can be configured as two 16-bit time rs, with selectable operat- ing modes. these timers are utilized by other peripheral modules such as: input capture output compare/simple pwm the following sections prov ide a detailed description, including setup and control re gisters, along with asso- ciated block diagrams for the operational modes of the timers. the 32-bit timer has the following modes: two independent 16-bit timers (timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) single 32-bit timer operation single 32-bit synchronous counter further, the following operational characteristics are supported: adc event trigger timer gate operation selectable prescaler settings timer operation during idle and sleep modes interrupt on a 32-bit period register match these operating modes are determined by setting the appropriate bit(s) in th e 16-bit t2con and t3con sfrs. for 32-bit timer/counter operation, timer2 is the ls word and timer3 is the ms word of the 32-bit timer. 16-bit mode: in the 16-bit mode, timer2 and timer3 can be configured as two independent 16-bit timers. each timer can be set up in either 16-bit timer mode or 16-bit synchronous counte r mode. see section 9.0, timer1 module, for detail s on these two operating modes. the only functional differ ence between timer2 and timer3 is that timer2 prov ides synchronization of the clock prescaler output. this is useful for high frequency external clock inputs. 32-bit timer mode: in the 32-bit timer mode, the timer increments on every instruction cycle up to a match value, preloaded into the combined 32-bit period regis- ter pr3/pr2, then resets to 0 and continues to count. for synchronous 32-bit reads of the timer2/timer3 pair, reading the ls word (tmr2 register) will cause the ms word to be read and latched into a 16-bit holding register, termed tmr3hld. for synchronous 32-bit writes, the holding register (tmr3hld) must first be written to. when followed by a write to the tmr2 register, the contents of tmr3hld will be transferred and latched into the msb of the 32-bit timer (tmr3). 32-bit synchronous counter mode: in the 32-bit synchronous counter mode, the timer increments on the rising edge of the appl ied external clock signal, which is synchronized with the internal phase clocks. the timer counts up to a ma tch value preloaded in the combined 32-bit period regist er pr3/pr2, then resets to ? 0 ? and continues. when the timer is configured for the synchronous counter mode of operation and the cpu goes into the idle mode, the timer will stop incrementing, unless the tsidl (t2con<13>) bit = 0 . if tsidl = 1 , the timer module logic will resume the incrementing sequence upon termination of the cpu idle mode. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: timer2 is a ?type b? timer and timer3 is a ?type c? timer. please refer to the appro- priate timer type in section 24.0 electrical characteristics of this document. note: for 32-bit timer operation, t3con control bits are ignored. only t2con control bits are used for setup and control. timer 2 clock and gate inputs are utilized for the 32-bit timer module, but an interrupt is generated with the timer3 interrupt flag (t3if) and the interrupt is enabled with the timer3 interrupt enable bit (t3ie).
DSPIC30F4011/4012 ds70135c-page 68 preliminary ? 2005 microchip technology inc. figure 10-1: 32-bit timer2/3 block diagram tmr3 tmr2 t3if equal comparator x 32 pr3 pr2 reset lsb msb event flag note: timer configuration bit t32, t2con(<3>) must be set to 1 for a 32-bit timer/counter operation. all control bits are respective to the t2con register. data bus<15:0> tmr3hld read tmr2 write tmr2 16 16 16 q q d ck tgate(t2con<6>) (t2con<6>) tgate 0 1 ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs 1 x 0 1 tgate 0 0 gate t2ck sync adc event trigger sync
? 2005 microchip technology inc. preliminary ds70135c-page 69 DSPIC30F4011/4012 figure 10-2: 16-bit timer2 block diagram figure 10-3: 16-bit timer3 block diagram ton sync pr2 t2if equal comparator x 16 tmr2 reset event flag q qd ck tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 gate t2ck sync ton pr3 t3if equal comparator x 16 tmr3 reset event flag q q d ck tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 adc event trigger sync note: the DSPIC30F4011/4012 devices do not have external pin i nputs to timer3. in these devices the following modes should not be used: 1. tcs = 1 2. tcs = 0 and tgate = 1 (gated time accumulation)
DSPIC30F4011/4012 ds70135c-page 70 preliminary ? 2005 microchip technology inc. 10.1 timer gate operation the 32-bit timer can be plac ed in the gated time accu- mulation mode. this mode allows the internal t cy to increment the respective time r when the gate input sig- nal (t2ck pin) is asserted high. control bit tgate (t2con<6>) must be set to enable this mode. when in this mode, timer2 is the orig inating clock source. the tgate setting is ignored fo r timer3. the timer must be enabled (ton = 1 ) and the timer clock source set to internal (tcs = 0 ). the falling edge of the exte rnal signal terminates the count operation, but does not reset the timer. the user must reset the timer in order to start counting from zero. 10.2 adc event trigger when a match occurs betw een the 32-bit timer (tmr3/ tmr2) and the 32-bit combin ed period register (pr3/ pr2), a special adc trigger event signal is generated by timer3. 10.3 timer prescaler the input clock (f osc /4 or external clock) to the timer has a prescale option of 1: 1, 1:8, 1:64, and 1:256 selected by control bits tckps<1:0> (t2con<5:4> and t3con<5:4>). for the 32 -bit timer operation, the originating clock source is timer2. the prescaler oper- ation for timer3 is not applicable in this mode. the prescaler counter is cleared when any of the following occurs: a write to the tmr2/tmr3 register clearing either of the ton (t2con<15> or t3con<15>) bits to ? 0 ? device reset such as por and bor however, if the time r is disabled (ton = 0 ), then the timer 2 prescaler cannot be reset, since the prescaler clock is halted. tmr2/tmr3 is not cleared when t2con/t3con is written. 10.4 timer operation during sleep mode during cpu sleep mode, th e timer will not operate, because the internal clocks are disabled. 10.5 timer interrupt the 32-bit timer module can generate an interrupt on period match, or on the falling edge of the external gate signal. when the 32-bit timer count matches the respective 32-bit period reg ister, or the falling edge of the external ?gate? signal is detected, the t3if bit (ifs0<7>) is asserted and an interrupt will be gener- ated if enabled. in this mode, the t3if interrupt flag is used as the source of the interrupt. the t3if bit must be cleared in software. enabling an interrupt is accomplished via the respective timer interrupt enable bit, t3ie (iec0<7>).
? 2005 microchip technology inc. preliminary ds70135c-page 71 DSPIC30F4011/4012 table 10-1: timer2/3 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state tmr2 0106 timer2 register uuuu uuuu uuuu uuuu tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) uuuu uuuu uuuu uuuu tmr3 010a timer3 register uuuu uuuu uuuu uuuu pr2 010c period register 2 1111 1111 1111 1111 pr3 010e period register 3 1111 1111 1111 1111 t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 0000 0000 0000 t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 0000 0000 0000 legend: u = uninitialized bit
DSPIC30F4011/4012 ds70135c-page 72 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 73 DSPIC30F4011/4012 11.0 timer4/5 module this section describes th e second 32-bit general purpose (gp) timer module (timer4/5) and associated operational modes. figure 11- 1 depicts the simplified block diagram of the 32-bit timer4/5 module. figure 11-2 and figure 11-3 sh ow timer4/5 configured as two independent 16-bit timers, timer4 and timer5, respectively. the timer4/5 module is similar in operation to the timer 2/3 module. however, there are some differences, which are as follows: the timer4/5 module does not support the adc event trigger feature timer4/5 can not be utilized by other peripheral modules such as input capture and output compare the operating modes of the timer4/5 module are determined by setting the appropriate bit(s) in the 16-bit t4con and t5con sfrs. for 32-bit timer/counter operation, timer4 is the ls word and timer5 is the ms word of the 32-bit timer. figure 11-1: 32-bit timer4/5 block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: timer4 is a ?type b? timer and timer5 is a ?type c? timer. please refer to the appro- priate timer type in section 24.0 electrical characteristics of this document. note: for 32-bit timer operation, t5con control bits are ignored. only t4con control bits are used for setup and control. timer4 clock and gate inputs are utilized for the 32-bit timer module, but an interrupt is generated with the timer5 interrupt flag (t5if) and the interrupt is enabled with the timer5 interrupt enable bit (t5ie). tmr5 tmr4 t5if equal comparator x 32 pr5 pr4 reset lsb msb event flag note: timer configuration bit t32, t4con(<3>) must be set to ? 1 ? for a 32-bit timer/counter operation. all control bits are respective to the t4con register. the DSPIC30F4011/4012 devices do not have external pin inputs to timer4 or timer5. in these devices the following modes should not be used: (1) tcs = 1, (2) tcs = 0 and (3) tgate = 1 (gated time accumulation) data bus<15:0> tmr5hld read tmr4 write tmr4 16 16 16 q q d ck tgate(t4con<6>) (t4con<6>) tgate 0 1 ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs 1 x 0 1 tgate 0 0 gate sync sync
DSPIC30F4011/4012 ds70135c-page 74 preliminary ? 2005 microchip technology inc. figure 11-2: 16-bit timer4 block diagram ton sync pr4 t4if equal comparator x 16 tmr4 reset event flag q q d ck tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 gate sync note: the DSPIC30F4011/4012 devices do not have external pin inputs to timer4 or timer5. in these devices the following modes should not be used: 1. tcs = 1 2. tcs = 0 and tgate = 1 (gated time accumulation)
? 2005 microchip technology inc. preliminary ds70135c-page 75 DSPIC30F4011/4012 figure 11-3: 16-bit timer5 block diagram ton pr5 t5if equal comparator x 16 tmr5 reset event flag q q d ck tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 adc event trigger sync note: the DSPIC30F4011/4012 devices do not have external pi n inputs to timer4 or timer5. in these devices the following mo des should not be used: 1. tcs = 1 2. tcs = 0 and tgate = 1 (gated time accumulation)
DSPIC30F4011/4012 ds70135c-page 76 preliminary ? 2005 microchip technology inc. table 11-1: timer4/5 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state tmr4 0114 timer 4 register uuuu uuuu uuuu uuuu tmr5hld 0116 timer 5 holding regis ter (for 32-bit operations only) uuuu uuuu uuuu uuuu tmr5 0118 timer 5 register uuuu uuuu uuuu uuuu pr4 011a period register 4 1111 1111 1111 1111 pr5 011c period register 5 1111 1111 1111 1111 t4con 011e ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t45 ?tcs ? 0000 0000 0000 0000 t5con 0120 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 0000 0000 0000 legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 77 DSPIC30F4011/4012 12.0 input capture module this section describes the input capture module and associated operational modes. the features provided by this module are useful in applications requiring frequency (period) and pulse measurement. figure 12-1 depicts a bloc k diagram of the input capture module. input capture is useful for such modes as: frequency/period/pulse measurements additional sources of external interrupts the key operational featur es of the input capture module are: simple capture event mode timer2 and timer3 mode selection interrupt on input capture event these operating modes are determined by setting the appropriate bits in the ic xcon register (where x = 1,2,...,n). the DSPIC30F4011/4012 devices have 4 capture channels. figure 12-1: input capture mode block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: the DSPIC30F4011/4012 devices have four capture inputs: ic1, ic2, ic7 and ic8. the naming of these four capture chan- nels is intentional and preserves software compatibility with other dspic devices. icxbuf prescaler icx icm<2:0> mode select 3 note: where ?x? is shown, reference is made to the regist ers or bits associated to the respective input capture channels 1 through n. 10 set flag pin icxif ictmr t2_cnt t3_cnt edge detection logic clock synchronizer 1, 4, 16 from gp timer module 16 16 fifo r/w logic ici<1:0> icbne, icov icxcon interrupt logic set flag icxif data bus
DSPIC30F4011/4012 ds70135c-page 78 preliminary ? 2005 microchip technology inc. 12.1 simple capture event mode the simple capture events in the dspic30f product family are: capture every falling edge capture every rising edge capture every 4th rising edge capture every 16th rising edge capture every rising and falling edge these simple input capture modes are configured by setting the appropriate bits icm<2:0> (icxcon<2:0>). 12.1.1 capture prescaler there are four input capture prescaler settings, speci- fied by bits icm<2:0> (icxcon<2:0>). whenever the capture channel is turned off, the prescaler counter will be cleared. in addition, any reset will clear the prescaler counter. 12.1.2 capture buffer operation each capture channel has an associated fifo buffer, which is four 16-bit words deep. there are two status flags, which provide status on the fifo buffer: icbfne - input capture buffer not empty icov - input capture overflow the icbfne will be set on the first input capture event and remain set until all capt ure events have been read from the fifo. as each word is read from the fifo, the remaining words are advanced by one position within the buffer. in the event that the fifo is full with four capture events and a fifth capture event occurs prior to a read of the fifo, an overflow c ondition will occur and the icov bit will be set to a logic ? 1 ?. the fifth capture event is lost and is not stored in the fifo. no additional events will be captured till all four events have been read from the buffer. if a fifo read is performed after the last read and no new capture event has be en received, the read will yield indeterminate results. 12.1.3 timer2 and timer3 selection mode each capture channel can se lect between one of two timers for the time base, timer2 or timer3. selection of the timer resource is accomplished through sfr bit ictmr (icxcon<7>). timer3 is the default timer resource available for the input capture module. 12.1.4 hall sensor mode when the input capture module is set for capture on every edge, rising and falling, icm<2:0> = 001 , the fol- lowing operations are performed by the input capture logic: the input capture interr upt flag is set on every edge, rising and falling. the interrupt on capture mode setting bits, ici<1:0>, is ignored, since every capture generates an interrupt. a capture overflow condit ion is not generated in this mode. 12.2 input capture operation during sleep and idle modes an input capture event will generate a device wake-up or interrupt, if enabled, if the device is in cpu idle or sleep mode. independent of the time r being enabled, the input capture module will wake-up from the cpu sleep or idle mode when a capture event occurs, if icm<2:0> = 111 and the interrupt enable bit is asserted. the same wake-up can generate an interr upt, if the conditions for processing the interrupt ha ve been satisfied. the wake-up feature is useful as a method of adding extra external pin interrupts. 12.2.1 input capture in cpu sleep mode cpu sleep mode allows i nput capture module opera- tion with reduced function ality. in the cpu sleep mode, the ici<1:0> bits are not applicable, and the input capture module can only function as an external interrupt source. the capture module must be configured for interrupt only on the rising edge (icm<2:0> = 111 ), in order for the input capture module to be used while the device is in sleep mode. the prescale settings of 4:1 or 16:1 are not applicable in this mode.
? 2005 microchip technology inc. preliminary ds70135c-page 79 DSPIC30F4011/4012 12.2.2 input capture in cpu idle mode cpu idle mode allows input capture module operation with full functionality. in the cpu idle mode, the interrupt mode selected by the ici<1:0> bits are applicable, as well as the 4:1 and 16:1 capture prescale settings, which are defined by control bits icm<2:0>. this mode requires the selected timer to be enabled. moreover, the icsidl bit must be asserted to a logic ? 0 ?. if the input capture module is defined as icm<2:0> = 111 in cpu idle mode, the in put capture pin will serve only as an external interrupt pin. 12.3 input capture interrupts the input capture channels ha ve the ability to generate an interrupt, based upon the selected number of cap- ture events. the selection nu mber is set by control bits ici<1:0> (icxcon<6:5>). each channel provides an in terrupt flag (icxif) bit. the respective capture channel in terrupt flag is located in the corresponding ifsx status register. enabling an interrupt is ac complished via the respec- tive capture channel interrupt enable (icxie) bit. the capture interrupt enable bit is located in the corresponding iec control register.
DSPIC30F4011/4012 ds70135c-page 80 preliminary ? 2005 microchip technology inc. table 12-1: input capture register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state ic1buf 0140 input 1 capture register uuuu uuuu uuuu uuuu ic1con 0142 ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic2buf 0144 input 2 capture register uuuu uuuu uuuu uuuu ic2con 0146 ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic7buf 0158 input 7 capture register uuuu uuuu uuuu uuuu ic7con 015a ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic8buf 015c input 8 capture register uuuu uuuu uuuu uuuu ic8con 015e ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 81 DSPIC30F4011/4012 13.0 output compare module this section describes th e output compare module and associated operational modes. the features pro- vided by this module are useful in applications requiring operational modes such as: generation of variable width output pulses power factor correction figure 13-1 depicts a bloc k diagram of the output compare module. the key operational features of the output compare module include: timer2 and timer3 selection mode simple output compare match mode dual output compare match mode simple pwm mode output compare during sleep and idle modes interrupt on output compare/pwm event these operating modes are determined by setting the appropriate bits in the 16-bit ocxcon sfr (where x = 1,2,3,...,n). the DSPIC30F4011/4012 devices have 4/2 compare channels, respectively. ocxrs and ocxr in the figure represent the dual compare registers. in the dual compare mode, the ocxr register is used for the first compare and ocxrs is used for the second compare. figure 13-1: output compare mode block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). ocxr comparator output logic q s r ocm<2:0> output enable ocx set flag bit ocxif ocxrs mode select 3 note: where ?x? is shown, reference is ma de to the registers associated with the respective output compare channels 1 through n. ocfa octsel 0 1 t2p2_match tmr2<15:0 tmr3<15:0> t3p3_match from gp timer module (for x = 1, 2, 3 or 4) 0 1
DSPIC30F4011/4012 ds70135c-page 82 preliminary ? 2005 microchip technology inc. 13.1 timer2 and timer3 selection mode each output compare channel can select between one of two 16-bit timers; timer2 or timer3. the selection of the timers is controlled by the octsel bit (ocxcon<3>). timer2 is the default timer resource for the output compare module. 13.2 simple output compare match mode when control bits ocm<2:0> (ocxcon<2:0>) = 001 , 010 or 011 , the selected output compare channel is configured for one of three simple output compare match modes: compare forces i/o pin low compare forces i/o pin high compare toggles i/o pin the ocxr register is used in these modes. the ocxr register is loaded with a value and is compared to the selected incrementing timer count. when a compare occurs, one of these compare match modes occurs. if the counter resets to zero before reaching the value in ocxr, the state of the ocx pin remains unchanged. 13.3 dual output compare match mode when control bits ocm<2:0> (ocxcon<2:0>) = 100 or 101 , the selected output compare channel is config- ured for one of two dual output compare modes, which are: single output pulse mode continuous output pulse mode 13.3.1 single pulse mode for the user to configure the module for the generation of a single output pulse, the following steps are required (assuming timer is off): determine instruction cycle time t cy . calculate desired pulse width value based on t cy . calculate time to start pul se from timer start value of 0x0000. write pulse width start and stop times into ocxr and ocxrs compare registers (x denotes channel 1, 2, ...,n). set timer period register to value equal to, or greater than, value in ocxrs compare register. set ocm<2:0> = 100 . enable timer, ton (txcon<15>) = 1 . to initiate another single pulse, issue another write to set ocm<2:0> = 100 . 13.3.2 continuous pulse mode for the user to configure t he module for the generation of a continuous stream of output pulses, the following steps are required: determine instruction cycle time t cy . calculate desired pulse value based on t cy . calculate timer to start pulse width from timer start value of 0x0000. write pulse width start and stop times into ocxr and ocxrs (x denotes channel 1, 2, ...,n) compare registers, respectively. set timer period register to value equal to, or greater than, value in ocxrs compare register. set ocm<2:0> = 101 . enable timer, ton (txcon<15>) = 1 . 13.4 simple pwm mode when control bits ocm<2:0> (ocxcon<2:0>) = 110 or 111 , the selected output co mpare channel is config- ured for the pwm mode of operation. when configured for the pwm mode of operation , ocxr is the main latch (read only) and ocxrs is the secondary latch. this enables glitchless pwm transitions. the user must perform the following steps in order to configure the output compare module for pwm operation: 1. set the pwm period by writing to the appropriate period register. 2. set the pwm duty cycle by writing to the ocxrs register. 3. configure the output compare module for pwm operation. 4. set the tmrx prescale value and enable the timer, ton (txcon<15>) = 1 . 13.4.1 input pin fault protection for pwm when control bits ocm<2:0> (ocxcon<2:0>) = 111 , the selected output compar e channel is again config- ured for the pwm mode of operation, with the addi- tional feature of input fault protection. while in this mode, if a logic 0 is detect ed on the ocfa/b pin, the respective pwm output pin is placed in the high imped- ance input state. the ocflt bit (ocxcon<4>) indi- cates whether a fault condition has occurred. this state will be maintained un til both of the following events have occurred: the external fault condition has been removed. the pwm mode has been re-enabled by writing to the appropriate control bits.
? 2005 microchip technology inc. preliminary ds70135c-page 83 DSPIC30F4011/4012 13.4.2 pwm period the pwm period is specified by writing to the prx reg- ister. the pwm period can be calculated using equation 13-1. equation 13-1: pwm period pwm frequency is defined as 1 / [pwm period]. when the selected tmrx is equal to its respective period register, prx, the following four events occur on the next increment cycle: tmrx is cleared. the ocx pin is set. - exception 1: if pwm duty cycle is 0x0000, the ocx pin will remain low. - exception 2: if duty cycle is greater than prx, the pin will remain high. the pwm duty cycle is latched from ocxrs into ocxr. the corresponding timer interrupt flag is set. see figure 13-1 for key pwm period comparisons. timer3 is referred to in the figure for clarity. figure 13-1: pwm output timing 13.5 output compare operation during cpu sleep mode when the cpu enters the sleep mode, all internal clocks are stopped. theref ore, when the cpu enters the sleep state, the output compare channel will drive the pin to the active stat e that was observed prior to entering the cpu sleep state. for example, if the pi n was high when the cpu entered the sleep state, the pin will remain high. like- wise, if the pin was low when the cpu entered the sleep state, the pin will remain low. in either case, the output compare module wi ll resume operation when the device wakes up. 13.6 output compare operation during cpu idle mode when the cpu enters the idle mode, the output compare module can operate with full functionality. the output compare channel will operate during the cpu idle mode if the ocsi dl bit (ocxcon<13>) is at logic 0 and the selected time base (timer2 or timer3) is enabled and the tsidl bit of the selected timer is set to logic 0 . 13.7 output compare interrupts the output compare channels have the ability to gener- ate an interrupt on a comp are match, for whichever match mode has been selected. for all modes except the pwm mode, when a compare event occurs, the respective interrupt flag (ocxif) is asserted and an interrupt w ill be generated, if enabled. the ocxif bit is located in the corresponding ifs status register, and must be cleared in software. the interrupt is enabled via the respective compare inter- rupt enable (ocxie) bit, loca ted in the corresponding iec control register. for the pwm mode, when an event occurs, the respec- tive timer interrupt flag (t 2if or t3if) is asserted and an interrupt will be generated , if enabled. the if bit is located in the ifs0 status register, and must be cleared in software. the interrupt is enabled via the respective timer interrupt enable bit (t2i e or t3ie), located in the iec0 control register. the output compare interrupt flag is never set during the pwm mode of operation. pwm period = [(prx) + 1] 4 t osc (tmrx prescale value) period duty cycle tmr3 = duty cycle (ocxr) tmr3 = duty cycle (ocxr) tmr3 = pr3 t3if = 1 (interrupt flag) ocxr = ocxrs tmr3 = pr3 (interrupt flag) ocxr = ocxrs t3if = 1
DSPIC30F4011/4012 ds70135c-page 84 preliminary ? 2005 microchip technology inc. table 13-1: output compare register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state oc1rs 0180 output compare 1 secondary register 0000 0000 0000 0000 oc1r 0182 output compare 1 main register 0000 0000 0000 0000 oc1con 0184 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc2rs 0186 output compare 2 secondary register 0000 0000 0000 0000 oc2r 0188 output compare 2 main register 0000 0000 0000 0000 oc2con 018a ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octse ocm<2:0> 0000 0000 0000 0000 oc3rs* 018c output compare 3 secondary register 0000 0000 0000 0000 oc3r* 018e output compare 3 main register 0000 0000 0000 0000 oc3con* 0190 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc4rs* 0192 output compare 4 secondary register 0000 0000 0000 0000 oc4r* 0194 output compare 4 main register 0000 0000 0000 0000 oc4con* 0196 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 legend: u = uninitialized bit, * = not available on dspic30f4012
? 2005 microchip technology inc. preliminary ds70135c-page 85 DSPIC30F4011/4012 14.0 quadrature encoder interface (qei) module this section describes the quadrature encoder inter- face (qei) module and asso ciated operational modes. the qei module provides the interface to incremental encoders for obtaining mechanical position data. the operational features of the qei include: three input channels fo r two phase signals and index pulse 16-bit up/down position counter count direction status position measurement (x2 and x4) mode programmable digital noise filters on inputs alternate 16-bit timer/counter mode quadrature encoder interface interrupts these operating modes are determined by setting the appropriate bits qeim<2:0> (qeicon<10:8>). figure 14-1 depicts the quad rature encoder interface block diagram. figure 14-1: quadrature enco der interface block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). 16-bit up/down counter comparator/ max count register quadrature programmable digital filter qea programmable digital filter indx up/down 3 encoder programmable digital filter qeb interface logic qeim<2:0> mode select 3 (poscnt) (maxcnt) qeiif event flag reset equal 2 t cy 1 0 tqcs tqckps<1:0> 2 1, 8, 64, 256 prescaler q q d ck tqgate qeim<2:0> synchronize det 1 0 sleep input 0 1 updn_src qeicon<11> zero detect note: in DSPIC30F4011/4012, the updn pin is not available. up/down logic bit can sti ll be polled by software.
DSPIC30F4011/4012 ds70135c-page 86 preliminary ? 2005 microchip technology inc. 14.1 quadrature encoder interface logic a typical incremental (a.k.a. optical) encoder has three outputs: phase a, phase b, and an index pulse. these signals are useful and often required in position and speed control of acim and sr motors. the two channels, phase a (qea) and phase b (qeb), have a unique relationship. if phase a leads phase b, then the direction (of the mo tor) is deemed positive or forward. if phase a lags phase b, then the direction (of the motor) is deemed negative or reverse. a third channel, termed index pulse, occurs once per revolution and is used as a reference to establish an absolute position. the in dex pulse coincides with phase a and phase b, both low. 14.2 16-bit up/down position counter mode the 16-bit up/down counter counts up or down on every count pulse, which is generated by the difference of the phase a and phase b input signals. the counter acts as an integrator, whose count value is proportional to position. the direction of the count is determined by the updn signal, which is generated by the quadrature encoder interface logic. 14.2.1 position counter error checking position count error checking in the qei is provided for and indicated by the cnterr bit (qeicon<15>). the error checking only applies when the position counter is configured for reset on the index pulse modes (qeim<2:0> = ? 110 ? or ? 100 ?). in these modes, the contents of the poscnt register is compared with the values (0xffff or maxcnt+ 1 , depending on direc- tion). if these values are detected, an error condition is generated by setting the cnterr bit and a qei count error interrupt is generated. the qei count error interrupt can be disabled by setting the ceid bit (dfltcon<8>). the position counter continues to count encoder edges after an error has been detected. the poscnt register continues to count up/down until a natural rollover/underflow . no interrupt is generated for the natural rollover/u nderflow event. the cnterr bit is a read/write bit and rese t in software by the user. 14.2.2 position counter reset the position counter reset enable bit, posres (qei<2>) controls whether the position counter is reset when the index pulse is detected. this bit is only applicable when qeim<2:0> = ? 100 ? or ? 110 ?. if the posres bit is set to ? 1 ?, then the position counter is reset when the index pulse is detected. if the posres bit is set to ? 0 ?, then the position counter is not reset when the index pulse is detected. the position counter will continue counting up or down, and will be reset on the rollover or underflow condition. when selecting the indx signal to reset the position counter (poscnt), the user has to specify the states on qea and qeb input pins. these states have to be matched in order for a reset to occur. these states are selected by the imv<1:0> bit in the dfltcon <10:9> register. the imv<1:0> (index match va lue) bit allows the user to specify the state of the qea and qeb input pins during an index pulse when the poscnt register is to be reset. in 4x quadrature count mode: imv1 = required state of phase b input signal for match on index pulse imv0 = required state of phase a input signal for match on index pulse in 2x quadrature count mode: imv1 = selects phase input signal for index state match (0 = phase a, 1 = phase b) imv0 = required state of the selected phase input signal for match on index pulse the interrupt is still gener ated on the detection of the index pulse and not on the position counter overflow/ underflow. 14.2.3 count direction status as mentioned in the previous section, the qei logic generates an updn signal, based upon the relation- ship between phase a and phas e b. in addition to the output pin, the state of this internal updn signal is supplied to a sfr bit updn (qeicon<11>) as a read only bit. note: qei pins are multiplexed with analog inputs. user must in sure that all qei associated pins are set as digital inputs in the adpcfg register.
? 2005 microchip technology inc. preliminary ds70135c-page 87 DSPIC30F4011/4012 14.3 position measurement mode there are two measurement modes which are sup- ported and are termed x2 and x4. these modes are selected by the qeim<2:0> mo de select bits located in sfr qeicon<10:8>. when control bits qeim<2:0> = 100 or 101 , the x2 measurement mode is select ed and the qe i logic only looks at the phase a input for the position counter increment rate. every risin g and falling edge of the phase a signal causes the position counter to be incre- mented or decremented. the phase b signal is still utilized for the determinatio n of the counter direction, just as in the x4 mode. within the x2 measurem ent mode, there are two variations of how the position counter is reset: 1. position counter reset by detection of index pulse, qeim<2:0> = 100 . 2. position counter reset by match with maxcnt, qeim<2:0> = 101 . when control bits qeim<2:0> = 110 or 111 , the x4 measurement mode is select ed and the qei logic looks at both edges of the phas e a and phase b input sig- nals. every edge of both signals causes the position counter to increment or decrement. within the x4 measurem ent mode, there are two variations of how the position counter is reset: 1. position counter reset by detection of index pulse, qeim<2:0> = 110 . 2. position counter reset by match with maxcnt, qeim<2:0> = 111 . the x4 measurement mode provides for finer resolu- tion data (more position c ounts) for determining motor position. 14.4 programmable digital noise filters the digital noise filter sect ion is responsible for reject- ing noise on the incoming ca pture or quadrature sig- nals. schmitt trigger inputs and a three-clock cycle delay filter combine to reje ct low level noise and large, short duration noise spikes th at typically occur in noise prone applications, such as a motor system. the filter ensures that the fi ltered output signal is not permitted to change unti l a stable value has been registered for three consecutive clock cycles. for the qea, qeb and indx pins, the clock divide fre- quency for the digital filter is programmed by bits qeck<2:0> (dfltcon<6:4>) and are derived from the base instruction cycle t cy . to enable the filter output for channels qea, qeb and indx, the qeout bit must be ? 1 ?. the filter network for all channels is disabled on por and bor. 14.5 alternate 16-bit timer/counter when the qei module is not configured for the qei mode qeim<2:0> = 001 , the module can be configured as a simple 16-bit timer/coun ter. the setup and control of the auxiliary timer is accomplished through the qeicon sfr register. this timer functions identically to timer1. the qea pin is us ed as the timer clock input. when configured as a time r, the poscnt register serves as the timer count register and the maxcnt register serves as the period register. when a timer/ period register match occur, the qei interrupt flag will be asserted. the only exception between the general purpose tim- ers and this timer is the added feature of external up/ down input select. when the updn pin is asserted high, the timer will increm ent up. when the updn pin is asserted low, the timer will be decremented. the updn control/status bit (qeicon<11>) can be used to select the count di rection state of the timer register. when updn = 1 , the timer will count up. when updn = 0 , the timer will count down. in addition, control bit updn_src (qeicon<0>) determines whether the time r count direction state is based on the logic state, written into the updn control/ status bit (qeicon<11>), or the qeb pin state. when updn_src = 1 , the timer count direction is controlled from the qeb pin. likewise, when updn_src = 0 , the timer count direction is controlled by the updn bit. 14.6 qei module operation during cpu sleep mode 14.6.1 qei operation during cpu sleep mode the qei module will be ha lted during the cpu sleep mode. 14.6.2 timer operation during cpu sleep mode during cpu sleep mode, the timer will not operate, because the internal clocks are disabled. note: changing the operational mode (i.e., from qei to timer or vice versa), will not affect the timer/position count register con- tents. note: this timer does not support the external asynchronous counter mode of operation. if using an external clock source, the clock will automatically be synchronized to the internal instruction cycle.
DSPIC30F4011/4012 ds70135c-page 88 preliminary ? 2005 microchip technology inc. 14.7 qei module operation during cpu idle mode since the qei module can function as a quadrature encoder interface, or as a 16-bit timer, the following section describes operati on of the module in both modes. 14.7.1 qei operation during cpu idle mode when the cpu is placed in the idle mode, the qei module will operate if the qeisidl bit (qeicon<13>) = 0 . this bit defaults to a logic ? 0 ? upon executing por and bor. for halting the qei module during the cpu idle mode, qeisidl should be set to ? 1 ?. 14.7.2 timer operation during cpu idle mode when the cpu is placed in th e idle mode and the qei module is configured in t he 16-bit timer mode, the 16-bit timer will oper ate if the qeisidl bit (qeicon<13>) = 0 . this bit defaults to a logic ? 0 ? upon executing por and bor. fo r halting the timer module during the cpu idle m ode, qeisidl should be set to ? 1 ?. if the qeisidl bit is cleared, the timer will function normally, as if the cpu idle mode had not been entered. 14.8 quadrature encoder interface interrupts the quadrature encoder in terface has the ability to generate an interrupt on occurrence of the following events: interrupt on 16-bit up/down position counter rollover/underflow detection of qualified index pulse, or if cnterr bit is set timer period match event (overflow/underflow) gate accumulation event the qei interrupt flag bi t, qeiif, is asserted upon occurrence of any of the above events. the qeiif bit must be cleared in software. qeiif is located in the ifs2 status register. enabling an interrupt is ac complished via the respec- tive enable bit, qeiie. the qeiie bit is located in the iec2 control register.
? 2005 microchip technology inc. preliminary ds70135c-page 89 DSPIC30F4011/4012 table 14-1: qei register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state qeicon 0122 cnterr ? qeisidl indx updn qeim2 qeim1 qeim0 swpab ? tqgate tqckps1 tqckps0 posres tqcs updn_src 0000 0000 0000 0000 dfltcon 0124 ? ? ? ? ? imv1 imv0 ceid qeout qeck2 qeck1 qeck0 ? ? ? ? 0000 0000 0000 0000 poscnt 0126 position counter<15:0> 0000 0000 0000 0000 maxcnt 0128 maximun count<15:0> 1111 1111 1111 1111 adpcfg 02a8 ? ? ? ? ? ? ? pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 legend: u = uninitialized bit
DSPIC30F4011/4012 ds70135c-page 90 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 91 DSPIC30F4011/4012 15.0 motor control pwm module this module simplifies the ta sk of generating multiple, synchronized pulse width modulated (pwm) outputs. in particular, the following power and motion control applications are support ed by the pwm module: three phase ac induction motor switched reluctance (sr) motor brushless dc (bldc) motor uninterruptible power supply (ups) the pwm module has the following features: 6 pwm i/o pins with 3 duty cycle generators up to 16-bit resolution ?on-the-fly? pwm frequency changes edge and center aligned output modes single pulse generation mode interrupt support for a symmetrical updates in center aligned mode output override control for electrically commutative motor (ecm) operation ?special event? comparator for scheduling other peripheral events fault pins to optionall y drive each of the pwm output pins to a defined state this module contains 3 duty cycle generators, num- bered 1 through 3. the mo dule has 6 pwm output pins, numbered pwm1h/pwm1l through pwm3h/pwm3l. the six i/o pins are grouped into high/low numbered pairs, denoted by the suffix h or l, respectively. for complementary loads, the low pwm pins are always the complement of the co rresponding high i/o pin. the pwm module allows se veral modes of operation which are beneficial for specific power control applications. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046).
DSPIC30F4011/4012 ds70135c-page 92 preliminary ? 2005 microchip technology inc. figure 15-1: pwm module block diagram pdc3 pdc3 buffer pwmcon1 ptper buffer pwmcon2 ptper ptmr comparator comparator channel 3 dead-time generator and ptcon sevtcmp comparator special event trigger ovdcon pwm enable and mode sfrs pwm manual control sfr channel 2 dead-time generator and channel 1 dead-time generator and pwm generator #2 pwm generator #1 pwm generator #3 sevtdir ptdir dtcon1 dead-time control sfrs special event postscaler pwm1l pwm1h pwm2l pwm2h note: details of pwm generator #1 and #2 not shown for clarity. 16-bit data bus pwm3l pwm3h fltacon fault pin control sfrs pwm time base output driver block flta override logic override logic override logic
? 2005 microchip technology inc. preliminary ds70135c-page 93 DSPIC30F4011/4012 15.1 pwm time base the pwm time base is provid ed by a 15-bit timer with a prescaler and postscaler. the time base is accessible via the ptmr sfr. ptmr<15> is a read only status bit, ptdir, that indicates the present count direction of the pwm time base. if ptdir is cleared, ptmr is counting upwards. if ptdir is set, ptmr is counting downwards. the pwm time base is configured via the ptcon sfr. the time base is enabled/disabled by setting/clearing the pten bit in the ptcon sfr. ptmr is not cleared when the pten bit is cleared in software. the ptper sfr sets the counting period for ptmr. the user must write a 15-bit value to ptper<14:0>. when the value in ptmr<14:0> matches the value in ptper<14:0>, the time base will either reset to 0, or reverse the count direction on the next occurring clock cycle. the action taken depends on the operating mode of the time base. the pwm time base can be configured for four different modes of operation: free running mode single shot mode continuous up/down count mode continuous up/down count mode with interrupts for double updates these four modes are selected by the ptmod<1:0> bits in the ptcon sfr. the up/down counting modes support center aligned pwm generation. the single shot mode allows the pwm module to support pulse control of certain electr onically commutative motors (ecms). the interrupt signals generat ed by the pwm time base depend on the mode selection bits (ptmod<1:0>) and the postscaler bits (ptops<3:0>) in the ptcon sfr. 15.1.1 free running mode in the free running mode, the pwm time base counts upwards until the value in th e time base period regis- ter (ptper) is matched. the ptmr register is reset on the following input clock e dge and the time base will continue to count upwards as long as the pten bit remains set. when the pwm time base is in the free running mode (ptmod<1:0> = 00 ), an interrupt event is generated each time a match with the ptper register occurs and the ptmr register is reset to zero. the postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. 15.1.2 single shot mode in the single shot counti ng mode, the pwm time base begins counting upwards when the pten bit is set. when the value in the ptmr register matches the ptper register, the ptmr re gister will be reset on the following input clock edge and the pten bit will be cleared by the hardware to halt the time base. when the pwm time base is in the single shot mode (ptmod<1:0> = 01 ), an interrupt event is generated when a match with the ptper register occurs, the ptmr register is reset to ze ro on the following input clock edge, and the pten bit is cleared. the postscaler selection bits have no effect in this mode of the timer . 15.1.3 continuous up/down counting modes in the continuous up/dow n counting modes, the pwm time base counts upwards until the value in the ptper register is matched. the timer will begin counting downwards on the followin g input clock edge. the ptdir bit in the ptcon sfr is read only and indicates the counting direction the ptdir bit is set when the timer counts downwards. in the up/down counting mode (ptmod<1:0> = 10 ), an interrupt event is generat ed each time the value of the ptmr register becomes zero and the pwm time base begins to count upwards. the postscaler selec- tion bits may be used in this mode of the timer to reduce the frequency of the interrupt events. note: if the period register is set to 0x0000, the timer will stop count ing, and the interrupt and the special event trigger will not be generated, even if the special event value is also 0x0000. the module will not update the period register, if it is already at 0x0000; therefore, the user must disable the module in order to update the period register.
DSPIC30F4011/4012 ds70135c-page 94 preliminary ? 2005 microchip technology inc. 15.1.4 double update mode in the double update mode (ptmod<1:0> = 11 ), an interrupt event is generated each time the ptmr regis- ter is equal to zero, as well as each time a period match occurs. the postscaler selection bits have no effect in this mode of the timer. the double update mode prov ides two additional func- tions to the user. first, t he control loop bandwidth is doubled because the pwm duty cycles can be updated, twice per period. second, asymmetrical cen- ter-aligned pwm waveform s can be generated, which are useful for minimizing ou tput waveform distortion in certain motor control applications. 15.1.5 pwm time base prescaler the input clock to ptmr (f osc /4), has prescaler options of 1:1, 1:4, 1:16, or 1:64, selected by control bits ptckps<1:0> in the ptcon sfr. the prescaler counter is cleared when any of the following occurs: a write to the ptmr register a write to the ptcon register any device reset the ptmr register is not cleared when ptcon is written. 15.1.6 pwm time base postscaler the match output of ptmr can optionally be post- scaled through a 4-bit postsc aler (which gives a 1:1 to 1:16 scaling). the postscaler counter is cleared when any of the following occurs: a write to the ptmr register a write to the ptcon register any device reset the ptmr register is not cleared when ptcon is written. 15.2 pwm period ptper is a 15-bit register and is used to set the count- ing period for the pwm time base. ptper is a double buffered register. the ptper buffer contents are loaded into the ptper register at the following instants: free running and single shot modes: when the ptmr register is reset to zero after a match with the ptper register. up/down counting modes : when the ptmr register is zero. the value held in the ptper buffer is automatically loaded into the ptper re gister when the pwm time base is disabled (pten = 0 ). the pwm period can be determined using equation 15-1: equation 15-1: pwm period if the pwm time base is conf igured for one of the up/ down count modes, the pwm period will be twice the value provided by equation 15-1. the maximum resolution (i n bits) for a given device oscillator and pwm frequency can be determined using equation 15-2: equation 15-2: pwm resolution 15.3 edge aligned pwm edge aligned pwm signals ar e produced by the module when the pwm time base is in the free running or sin- gle shot mode. for edge al igned pwm outputs, the out- put has a period specified by the value in ptper and a duty cycle specified by the appropriate duty cycle regis- ter (see figure 15-2). the pwm output is driven active at the beginning of the period (ptmr = 0 ) and is driven inactive when the value in the duty cycle register matches ptmr. if the value in a particular duty cycle register is zero, then the output on the co rresponding pwm pin will be inactive for the entire pwm period. in addition, the out- put on the pwm pin will be active for the entire pwm period if the value in the du ty cycle register is greater than the value held in the ptper register. figure 15-2: edge aligned pwm note: programming a value of 0x0001 in the period register could generate a continu- ous interrupt pulse, and hence, must be avoided. t pwm = t cy (ptper + 1) (ptmr prescale value) resolution = log (2 t pwm / t cy ) log (2) period duty cycle 0 ptper ptmr value new duty cycle latched
? 2005 microchip technology inc. preliminary ds70135c-page 95 DSPIC30F4011/4012 15.4 center aligned pwm center aligned pwm signals are produced by the mod- ule when the pwm time base is configured in an up/ down counting mode (see figure 15-3). the pwm compare output is driven to the active state when the value of the duty cycle register matches the value of ptmr and the pw m time base is counting downwards (ptdir = 1 ). the pwm compare output is driven to the inactive stat e when the pwm time base is counting upwards (ptdir = 0 ) and the value in the ptmr register matches the duty cycle value. if the value in a particular duty cycle register is zero, then the output on the co rresponding pwm pin will be inactive for the entire pwm period. in addition, the out- put on the pwm pin will be active for the entire pwm period if the value in the du ty cycle register is equal to the value held in the ptper register. figure 15-3: center aligned pwm 15.5 pwm duty cycle comparison units there are three 16-bit spe cial function registers (pdc1, pdc2 and pdc3) used to spe cify duty cycle values for the pwm module. the value in each duty cycle register determines the amount of time that the pwm output is in the active state. the duty cycle registers are 16-bits wide. the ls bit of a duty cycle regist er determines whether the pwm edge occurs in the beginning. thus, the pwm resolution is effectively doubled. 15.5.1 duty cycle register buffers the three pwm duty cycle registers are double buff- ered to allow glitchless updates of the pwm outputs. for each duty cycle, there is a duty cycle register that is accessible by the user a nd a second duty cycle reg- ister that holds the actual compare value used in the present pwm period. for edge aligned pwm outpu t, a new duty cycle value will be updated whenever a match with the ptper reg- ister occurs and ptmr is reset. the contents of the duty cycle buffers are auto matically loaded into the duty cycle registers when th e pwm time base is dis- abled (pten = 0 ) and the udis bit is cleared in pwmcon2. when the pwm time base is in the up/down counting mode, new duty cycle values are updated when the value of the ptmr register is zero and the pwm time base begins to count upwards. the contents of the duty cycle buffers are automat ically loaded into the duty cycle registers when the pwm time base is disabled (pten = 0 ). when the pwm time base is in the up/down counting mode with double updates, ne w duty cycle values are updated when the value of th e ptmr register is zero, and when the value of the pt mr register matches the value in the ptper register. the contents of the duty cycle buffers are automat ically loaded into the duty cycle registers when the pwm time base is disabled (pten = 0 ). 15.6 complementary pwm operation in the complementary mode of operation, each pair of pwm outputs is obtained by a complementary pwm signal. a dead-time may be optionally inserted during device switching, when both outputs are inactive for a short period (refer to section 15.7). in complementary mode, the duty cycle comparison units are assigned to the pwm outputs as follows: pdc1 register controls pwm1h/pwm1l outputs pdc2 register controls pwm2h/pwm2l outputs pdc3 register controls pwm3h/pwm3l outputs the complementary mode is selected for each pwm i/o pin pair by clearing the appropriate pmodx bit in the pwmcon1 sfr. the pwm i/o pins are set to complementary mode by def ault upon a device reset. 0 ptper ptmr value period period/2 duty cycle
DSPIC30F4011/4012 ds70135c-page 96 preliminary ? 2005 microchip technology inc. 15.7 dead-time generators dead-time generation may be provided when any of the pwm i/o pin pairs are operating in the comple- mentary output mode. th e pwm outputs use push- pull drive circuits. due to th e inability of the power out- put devices to switch instan taneously, some amount of time must be provided between the turn off event of one pwm output in a complementary pair and the turn on event of the other transistor. the pwm module allows two different dead-times to be programmed. these two dea d-times may be used in one of two methods described below to increase user flexibility: the pwm output signals can be optimized for dif- ferent turn off times in the high side and low side transistors in a complementary pair of transistors. the first dead-time is in serted between the turn off event of the lower transistor of the complemen- tary pair and the turn on event of the upper tran- sistor. the second dead-time is inserted between the turn off event of th e upper transistor and the turn on event of the lower transistor. the two dead-times can be assigned to individual pwm i/o pin pairs. this operating mode allows the pwm module to drive different transistor/load combinations with each complementary pwm i/o pin pair. 15.7.1 dead-time generators each complementary output pair for the pwm module has a 6-bit down counter that is used to produce the dead-time insertion. as shown in figure 15-4, each dead-time unit has a rising and falling edge detector connected to the duty cy cle comparison output. 15.7.2 dead-time ranges the amount of dead-time provided by the dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value. four input clock prescaler selections have been pro- vided to allow a suitable ra nge of dead-time, based on the device operating freque ncy. the dead-time clock prescaler values are selected using the dtaps<1:0> control bits in the dtcon1 sfr. one of four clock prescaler options (t cy , 2t cy , 4t cy or 8t cy ) may be selected. after the prescaler value is selected, the dead-time is adjusted by loading 6-bit unsigned values into the dtcon1 sfr. the dead-time unit prescaler is cleared on the following events: on a load of the down ti mer due to a duty cycle comparison edge event. on a write to the dtcon1 register. on any device reset. figure 15-4: dead-time timing diagram note: the user should not modify the dtcon1 value while the pwm module is operating (pten = 1 ). unexpected results may occur. duty cycle generator pwmxh pwmxl dead time a (active) dead time a (inactive)
? 2005 microchip technology inc. preliminary ds70135c-page 97 DSPIC30F4011/4012 15.8 independent pwm output an independent pwm output mode is required for driv- ing certain types of loads. a particular pwm output pair is in the independent ou tput mode when the corre- sponding pmod bit in the pwmcon1 register is set. no dead-time control is implemented between adjacent pwm i/o pins when the modu le is operating in the independent mode and both i/o pins are allowed to be active simultaneously. in the independent mode, ea ch duty cycle generator is connected to both of the pwm i/o pins in an output pair. by using the associated duty cycle register and the appropriate bits in the ovdcon register, the user may select the following si gnal output options for each pwm i/o pin operating in the independent mode: i/o pin outputs pwm signal i/o pin inactive i/o pin active 15.9 single pulse pwm operation the pwm module produces single pulse outputs when the ptcon control bits ptmod<1:0> = 10 . only edge aligned outputs may be pr oduced in the single pulse mode. in single pulse mode, the pwm i/o pin(s) are driven to the active state when the pten bit is set. when a match with a duty cycle register occurs, the pwm i/o pin is driven to th e inactive state. when a match with the ptper regist er occurs, the ptmr reg- ister is cleared, all active pwm i/o pins are driven to the inactive state, the pten bit is cleared, and an interrupt is generated. 15.10 pwm output override the pwm output override bits allow the user to manu- ally drive the pwm i/o pins to specified logic states, independent of the duty cycle comparison units. all control bits associated with the pwm output over- ride function are contained in the ovdcon register. the upper half of the ovdcon register contains six bits, povdxh<3:1> and povdxl<3:1>, that determine which pwm i/o pins will be overridden. the lower half of the ovdcon register contains six bits, poutxh<3:1> and poutxl<3:1>, that determine the state of the pwm i/o pins when a particular output is overridden via the povd bits. 15.10.1 complementary output mode when a pwmxl pin is driven active via the ovdcon register, the output signal is forced to be the comple- ment of the corresponding pwmxh pin in the pair. dead-time insertion is st ill performed when pwm channels are overridden manually. 15.10.2 override synchronization if the osync bit in the pwmc on2 register is set, all output overrides performed via the ovdcon register are synchronized to the pwm time base. synchronous output overrides occur at the following times: edge aligned mode, when ptmr is zero. center aligned modes, when ptmr is zero and when the value of ptmr matches ptper.
DSPIC30F4011/4012 ds70135c-page 98 preliminary ? 2005 microchip technology inc. 15.11 pwm output and polarity control there are three device configuration bits associated with the pwm module that provide pwm output pin control: hpol configuration bit lpol configuration bit pwmpin configuration bit these three bits in the fporbor configuration regis- ter (see section 21) work in conjunction with the three pwm enable bits (pwmen<3:1>) located in the pwmcon1 sfr. the configuration bits and pwm enable bits ensure that the pwm pins are in the correct states after a device reset occurs. the pwmpin con- figuration fuse allows the pwm module outputs to be optionally enabled on a de vice reset. if pwmpin = 0 , the pwm outputs will be drive n to their inactive states at reset. if pwmpin = 1 (default), the pwm outputs will be tri-stated. the hpol bi t specifies the polarity for the pwmxh outputs, whereas the lpol bit specifies the polarity for the pwmxl outputs. 15.11.1 output pin control the pen<3:1>h and pen<3:1>l control bits in the pwmcon1 sfr enable each high pwm output pin and each low pwm output pin, respectively. if a partic- ular pwm output pin not en abled, it is treated as a general purpose i/o pin. 15.12 pwm fault pin there is one fault pin (flt a) associated with the pwm module. when asserted, these pins can option- ally drive each of the pwm i/o pins to a defined state. 15.12.1 fault pin enable bits the fltacon sfr has 3 control bits that determine whether a particular pair of pwm i/o pins is to be controlled by the fault input pin. to enable a specific pwm i/o pin pair for fault overrides, the corresponding bit should be set in the fltacon register. if all enable bits are cleared in the fltacon register, then the corresponding faul t input pin has no effect on the pwm module and the pin may be used as a general purpose interrupt or i/o pin. 15.12.2 fault states the fltacon special function register has 6 bits that determine the state of each pwm i/o pin when it is overridden by a fault input. when these bits are cleared, the pwm i/o pin is dr iven to the inactive state. if the bit is set, the pwm i/o pin will be driven to the active state. the active and inactive states are refer- enced to the polarity defi ned for each pwm i/o pin (hpol and lpol polarity control bits). a special case exists when a pwm module i/o pair is in the complementary mode and both pins are pro- grammed to be active on a fault condition. the pwmxh pin always has priority in the complementary mode, so that both i/o pins cannot be driven active simultaneously. 15.12.3 fault input modes the fault input pin has two modes of operation: latched mode: when the fault pin is driven low, the pwm outputs will go to the states defined in the fltacon register. the pwm outputs will remain in this state until the fault pin is driven high and the correspond ing interrupt flag has been cleared in software . when both of these actions have occurred, the pwm outputs will return to normal operati on at the beginning of the next pwm cycle or ha lf-cycle boundary. if the interrupt flag is cleared before the fault condi- tion ends, the pwm modul e will wait until the fault pin is no longer asserted, to restore the outputs. cycle-by-cycle mode: when the fault input pin is driven low, the pwm outputs remain in the defined fault states for as long as the fault pin is held low. after the fault pin is driven high, the pwm outputs return to normal operation at the beginning of the foll owing pwm cycle or half-cycle boundary. the operating mode for the fault input pin is selected using the fltam control bit in the fltacon special function register. the fault pin can be contro lled manually in software. note: the fault pin logic can operate indepen- dent of the pwm logic. if all the enable bits in the fltacon register are cleared, then the fault pin could be used as a general purpose interrupt pin. the fault pin has an interrupt vector, in terrupt flag bit and interrupt priority bits associated with it.
? 2005 microchip technology inc. preliminary ds70135c-page 99 DSPIC30F4011/4012 15.13 pwm update lockout for a complex pwm applicati on, the user may need to write up to three duty cycle registers and the time base period register, ptper, at a given time. in some appli- cations, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. the pwm update lockout feat ure is enabled by setting the udis control bit in t he pwmcon2 sfr. the udis bit affects all duty cycle bu ffer registers and the pwm time base period buff er, ptper. no duty cycle changes or period va lue changes will have effect while udis = 1 . 15.14 pwm special event trigger the pwm module has a s pecial event trigger that allows a/d conversions to be synchronized to the pwm time base. the a/d sampling and conversion time may be programmed to occur at any point within the pwm period. the special event trig ger allows the user to min- imize the delay between the time when a/d conversion results are acquired and the time when the duty cycle value is updated. the pwm special event trigger has a sfr named sevtcmp, and five control bits to control its operation. the ptmr value for which a special event trigger should occur is loaded in to the sevtcmp register. when the pwm time base is in an up/down counting mode, an additional control bi t is required to specify the counting phase for the special event trigger. the count phase is selected using the sevtdir control bit in the sevtcmp sfr. if the sevtdir bit is cleared, the spe- cial event trigger will occur on the upward counting cycle of the pwm time base. if the sevtdir bit is set, the special event trigger wi ll occur on the downward count cycle of the pwm time base. the sevtdir control bit has no effect unless the pwm time base is configured for an up/down counting mode. 15.14.1 special event trigger postscaler the pwm special event trig ger has a postscaler that allows a 1:1 to 1:16 postscale ratio. the postscaler is configured by writing the sevops<3:0> control bits in the pwmcon2 sfr. the special event output postscaler is cleared on the following events: any write to the sevtcmp register any device reset 15.15 pwm operation during cpu sleep mode the fault a input pin has th e ability to wake the cpu from sleep mode. the pwm module generates an interrupt if the fault pin is driven low while in sleep. 15.16 pwm operation during cpu idle mode the ptcon sfr contains a ptsidl control bit. this bit determines if the pwm module will continue to operate or stop when the device enters idle mode. if ptsidl = 0 , the module will cont inue to operate. if ptsidl = 1 , the module will stop operation as long as the cpu remains in idle mode.
DSPIC30F4011/4012 ds70135c-page 100 preliminary ? 2005 microchip technology inc. table 15-1: 6-output pwm register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state ptcon 01c0 pten ?ptsidl ? ? ? ? ? ptops<3:0> ptckps<1:0> ptmod<1:0> 0000 0000 0000 0000 ptmr 01c2 ptdir pwm timer count value 0000 0000 0000 0000 ptper 01c4 ? pwm time base period register 0000 0000 0000 0000 sevtcmp 01c6 sevtdir pwm special event compare register 0000 0000 0000 0000 pwmcon1 01c8 ? ? ? ? ? ptmod3 ptmod2 ptmod1 ? pen3h pen2h pen1h ? pen3l pen2l pen1l 0000 0000 1111 1111 pwmcon2 01ca ? ? ? ? sevops<3:0> ? ? ? ? ? ? osync udis 0000 0000 0000 0000 dtcon1 01cc ? ? ? ? ? ? ? ? dtaps<1:0> dead-time a value 0000 0000 0000 0000 fltacon 01d0 ? ? faov3h faov3l faov2h faov2l faov1h faov1l fltam ? ? ? ? faen3 faen2 faen1 0000 0000 0000 0000 ovdcon 01d4 ? ? povd3h povd3l povd2h povd2l povd1h povd1l ? ? pout3h pout3l pout2h pout2l pout1h pout1l 1111 1111 0000 0000 pdc1 01d6 pwm duty cycle #1 register 0000 0000 0000 0000 pdc2 01d8 pwm duty cycle #2 register 0000 0000 0000 0000 pdc3 01da pwm duty cycle #3 register 0000 0000 0000 0000 legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 101 DSPIC30F4011/4012 16.0 spi? module the serial peripheral interface (spi) module is a syn- chronous serial interface. it is useful for communicating with other peripheral devices such as eeproms, shift registers, display drivers and a/d converters, or other microcontrollers. it is compatible with motorola's spi and siop interfaces. 16.1 operating function description the spi module consists of a 16-bit shift register, spi1sr, used for shifting data in and out, and a buffer register, spi1buf. a control register, spi1con, configures the module. additi onally, a status register, spi1stat, indicates various status conditions. the serial interface consists of 4 pins: sdi1 (serial data input), sdo1 (serial data output), sck1 (shift clock input or output), and ss1 (active low slave select). in master mode operation, sck is a clock output, but in slave mode, it is a clock input. a series of eight (8) or sixt een (16) cloc k pulses shifts out bits from the spi1sr to sdo1 pin and simulta- neously shifts in data from sdi1 pin. an interrupt is generated when the transfer is complete and the cor- responding interrupt flag bi t (spi1if) is set. this inter- rupt can be disabled through an interrupt enable bit (spi1ie). the receive operation is double buffered. when a complete byte is received, it is transferred from spi1sr to spi1buf. if the receive buffer is fu ll when new data is being transferred from spi1sr to spi1buf, the module will set the spirov bit, indicating an overflow condition. the transfer of the data from spi1sr to spi1buf will not be completed and the new data will be lost. the module will not respond to scl transitions while spirov is 1 , effectively disabling the module until spi1buf is read by user software. transmit writes are also double buffered. the user writes to spi1buf. when th e master or slave transfer is completed, the conten ts of the shift register (spi1sr) is moved to the re ceive buffer. if any trans- mit data has been written to the buffer register, the contents of the transmit buffer are moved to spi1sr. the received data is thus placed in spi1buf and the transmit data in spi1sr is ready for the next transfer. in master mode, the clock is generated by prescaling the system clock. data is transmitted as soon as a value is written to spi1buf. the interrupt is generated at the middle of the transfer of the last bit. in slave mode, data is tr ansmitted and received as external clock pulses appear on sck. again, the inter- rupt is generated when the la st bit is latched. if ssx control is enabled, then transmission and reception are enabled only when ssx = low. the sdox output will be disabled in ssx mode with ssx high. the clock provided to the module is (f osc /4). this clock is then prescaled by the primary (ppre<1:0>) and the secondary (spre<2:0> ) prescale factors. the cke bit determines whether tr ansmit occurs on transi- tion from active clock state to idle clock state, or vice versa. the ckp bit selects th e idle state (high or low) for the clock. 16.1.1 word and byte communication a control bit, mode16 (spi1con<10>), allows the module to communicate in ei ther 16-bit or 8-bit mode. 16-bit operation is identical to 8-bit operation, except that the number of bits tran smitted is 16 instead of 8. the user software must d isable the module prior to changing the mode16 bit. the spi module is reset when the mode16 bit is changed by the user. a basic difference between 8-bi t and 16-bit operation is that the data is transmitted out of bit 7 of the spixsr for 8-bit operation, and data is transmitted out of bit 15 of the spixsr for 16-bit operati on. in both modes, data is shifted into bit 0 of the spixsr. 16.1.2 sdo1 disable a control bit, dissdo, is provided to the spi1con register to allow the sdo1 output to be disabled. this will allow the spi module to be connected in an input only configuration. sdo can also be used for general purpose i/o. 16.2 framed spi support the module supports a ba sic framed spi protocol in master or slave mode. the control bit frmen enables framed spi support and causes the ss1 pin to perform the frame synchronization pulse (fsync) function. the control bit spifsd determines whether the ss1 pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). the frame pulse is an active high pulse for a single spi clock cycle. when frame synchronization is enabled, the data transm ission starts only on the subsequent transmit edge of the spi clock. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: both the transmit buffer (spi1txb) and the receive buffer (spi1rxb) are mapped to the same register address, spi1buf.
DSPIC30F4011/4012 ds70135c-page 102 preliminary ? 2005 microchip technology inc. figure 16-1: spi block diagram figure 16-2: spi master/slave connection note: in dspic30f4012, the ss1 pin is not available. read write internal data bus sdi1 sdo1 ss1 sck1 spi1sr spi1buf bit0 shift clock edge select f cy primary 1, 4, 16, 64 enable master clock prescaler secondary prescaler 1,2,4,6,8 ss & fsync control clock control transmit spi1buf receive serial input buffer (spixbuf) shift register (spixsr) msb lsb sdox sdix processor 1 sckx spi master serial input buffer (spiybuf) shift register (spiysr) lsb msb sdiy sdoy processor 2 scky spi slave serial clock note: x = 1 or 2, y = 1 or 2.
? 2005 microchip technology inc. preliminary ds70135c-page 103 DSPIC30F4011/4012 16.3 slave select synchronization the ss1 pin allows a synchronous slave mode. the spi must be configured in spi slave mode, with ss1 pin control enabled (ssen = 1 ). when the ss1 pin is low, transmission and reception are enabled, and the sdo1 pin is driven. when ss1 pin goes high, the sdo1 pin is no longer driven. also, the spi module is re-synchronized, and all coun ters/control circuitry are reset. therefore, when the ss1 pin is asserted low again, transmission/reception will begin at the ms bit, even if ss1 had been de-asserted in the middle of a transmit/receive. note that in dspic30f4012, the ss1 pin is not available. 16.4 spi operation during cpu sleep mode during sleep mode, the spi module is shut-down. if the cpu enters sleep mode while an spi transaction is in progress, then the tr ansmission and reception is aborted. the transmitter and receiver will stop in sleep mode. however, register contents are not affected by entering or exiting sleep mode. 16.5 spi operation during cpu idle mode when the device enters idle mode, all clock sources remain functional. the sp isidl bit (spi1stat<13>) selects if the spi module will stop or continue on idle. if spisidl = 0 , the module will continue to operate when the cpu enters id le mode. if spisidl = 1 , the module will stop when the cpu enters idle mode.
DSPIC30F4011/4012 ds70135c-page 104 preliminary ? 2005 microchip technology inc. table 16-1: spi1 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state spi1stat 0220 spien ? spisidl ? ? ? ? ? ? spirov ? ? ? ? spitbf spirbf 0000 0000 0000 0000 spi1con 0222 ? frmen spifsd ? dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 0000 0000 0000 spi1buf 0224 transmit and receive buffer 0000 0000 0000 0000 legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 105 DSPIC30F4011/4012 17.0 i 2 c? module the inter-integrated circuit (i 2 c) module provides complete hardware support for both slave and multi- master modes of the i 2 c serial communication standard, with a 16-bit interface. this module offers the following key features: i 2 c interface supporting both master and slave operation. i 2 c slave mode supports 7 and 10-bit address. i 2 c master mode supports 7 and 10-bit address. i 2 c port allows bi-directional transfers between master and slaves. serial clock synchronization for i 2 c port can be used as a handshake mech anism to suspend and resume serial transfer (sclrel control). i 2 c supports multi-master operation; detects bus collision and will arbitrate accordingly. 17.1 operating function description the hardware fully implements all the master and slave functions of the i 2 c standard and fa st mode specifica- tions, as well as 7 and 10-bit addressing. thus, the i 2 c module can operate either as a slave or a master on an i 2 c bus. 17.1.1 various i 2 c modes the following types of i 2 c operation are supported: i 2 c slave operation with 7-bit address i 2 c slave operation with 10-bit address i 2 c master operation with 7 or 10-bit address see the i 2 c programmer?s model in figure 17-1. 17.1.2 pin configuration in i 2 c mode i 2 c has a 2-pin interface; pin scl is clock and pin sda is data. 17.1.3 i 2 c registers i2ccon and i2cstat are control and status registers, respectively. the i2ccon regist er is readable and writ- able. the lower 6 bits of i2cstat are read only. the remaining bits of the i2cstat are read/write. i2crsr is the shift register used for shifting data, whereas i2crcv is the buffer register to which data bytes are written, or from which data bytes are read. i2crcv is the receive buffer, as shown in figure 17-1. i2ctrn is the transmit register to which bytes are written during a transmit operation, as shown in figure 17-2. the i2cadd register holds t he slave address. a status bit, add10, indicates 10 -bit address mode. the i2cbrg acts as the baud ra te generator reload value. in receive operations, i2crsr and i2crcv together form a double buffered receiver. when i2crsr receives a complete byte, it is transferred to i2crcv and an interrupt pulse is generated. during transmission, the i2ctrn is not double buffered. figure 17-1: programmer?s model note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: following a restart condition in 10-bit mode, the user only needs to match the first 7-bit address. bit 7 bit 0 i2crcv (8 bits) bit 7 bit 0 i2ctrn (8 bits) bit 8 bit 0 i2cbrg (9 bits) bit 15 bit 0 i2ccon (16-bits) bit 15 bit 0 i2cstat (16-bits) bit 9 bit 0 i2cadd (10-bits)
DSPIC30F4011/4012 ds70135c-page 106 preliminary ? 2005 microchip technology inc. figure 17-2: i 2 c block diagram i2crsr i2crcv internal data bus scl sda shift match detect i2cadd start and stop bit detect clock addr_match clock stretching i2ctrn lsb shift clock write read brg down i2cbrg reload control f cy start, restart, stop bit generate write read acknowledge generation collision detect write read write read i2ccon write read i2cstat control logic read lsb counter
? 2005 microchip technology inc. preliminary ds70135c-page 107 DSPIC30F4011/4012 17.2 i 2 c module addresses the i2cadd register contains the slave mode addresses. the register is a 10-bit register. if the a10m bit (i2ccon<10>) is ? 0 ?, the address is interpreted by the module as a 7-bit address. when an address is received, it is compared to the 7 ls bits of the i2cadd register. if the a10m bit is ? 1 ?, the address is assumed to be a 10-bit address. when an address is received, it will be compared with the binary value ? 11110 a9 a8 ? (where a9 and a8 are two most signific ant bits of i2cadd). if that value matches, the ne xt address will be compared with the least significant 8 bi ts of i2cadd, as specified in the 10-bit addressing protocol. the 7-bit i 2 c slave addresses supported by the dspic30f are shown in table 17-1. table 17-1: 7-bit i 2 c slave addresses 17.3 i 2 c 7-bit slave mode operation once enabled (i2cen = 1 ), the slave module will wait for a start bit to occur (i.e., the i 2 c module is ?idle?). following the detection of a start bit, 8 bits are shifted into i2crsr and the a ddress is compared against i2cadd. in 7-bit mode (a10m = 0 ), bits i2cadd<6:0> are compared against i2crsr<7:1> and i2crsr<0> is the r_w bit. all incoming bits are sampled on the rising edge of scl. if an address match occurs , an acknowledgement will be sent, and the slave event interrupt flag (si2cif) is set on the falling ed ge of the ninth (ack ) bit. the address match does not affect the contents of the i2crcv buffer or the rbf bit. 17.3.1 slave transmission if the r_w bit received is a ? 1 ?, then the serial port will go into transmit mode. it will send ack on the ninth bit and then hold scl to ? 0 ? until the cpu responds by writ- ing to i2ctrn. scl is released by setting the sclrel bit, and 8 bits of data are shifted out. data bits are shifted out on the falling edge of scl, such that sda is valid during scl high (see timing diagram). the inter- rupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ack received from the master. 17.3.2 slave reception if the r_w bit received is a ? 0 ? during an address match, then receive mode is initiated. incoming bits are sampled on the rising edge of scl. after 8 bits are received, if i2crcv is not full or i2cov is not set, i2crsr is transferred to i2crcv. ack is sent on the ninth clock. if the rbf flag is set, indicating that i2crcv is still holding data from a previous operation (rbf = 1 ), then ack is not sent; however, the interrupt pulse is gener- ated. in the case of an overflow, the contents of the i2crsr are not loaded into the i2crcv. 17.4 i 2 c 10-bit slave mode operation in 10-bit mode, the basic receive and transmit opera- tions are the same as in the 7-bit mode. however, the criteria for address match is more complex. the i 2 c specification dictates that a slave must be addressed for a writ e operation, with two address bytes following a start bit. the a10m bit is a control bi t that signifies that the address in i2cadd is a 10-b it address rather than a 7-bit address. the address detection protocol for the first byte of a message address is identical for 7-bit and 10-bit messages, but th e bits being compared are different. i2cadd holds the entire 10-bit address. upon receiv- ing an address following a start bit, i2crsr <7:3> is compared against a literal ? 11110 ? (the default 10-bit address) and i2crsr<2:1> are compared against i2cadd<9:8>. if a match occurs and if r_w = 0 , the interrupt pulse is sent. the add10 bit will be cleared to indicate a partial address match. if a match fails or r_w = 1 , the add10 bit is cle ared and the module returns to the idle state. the low byte of the address is then received and com- pared with i2cadd<7:0>. if an address match occurs, the interrupt pulse is gener ated and the add10 bit is set, indicating a complete 10 -bit address match. if an address match did not occur, the add10 bit is cleared and the module returns to the idle state. 17.4.1 10-bit mode slave transmission once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as "prior_addr_match"), th e master can begin sending data bytes for a sl ave reception operation. 0x00 general call address or start byte 0x01-0x03 reserved 0x04-0x77 valid 7-bit addresses 0x78-0x7b valid 10-bit add resses (lower 7 bits) 0x7c-0x7f reserved note: the i2crcv will be lo aded if the i2cov bit = 1 and the rbf flag = 0 . in this case, a read of the i2crcv was performed, but the user did not clear the state of the i2cov bit before the next receive occurred. the acknowledgement is not sent (ack = 1 ) and the i2crcv is updated.
DSPIC30F4011/4012 ds70135c-page 108 preliminary ? 2005 microchip technology inc. 17.4.2 10-bit mode slave reception once addressed, the master can generate a repeated start, reset the high byte of the address and set the r_w bit without generating a st op bit, thus initiating a slave transmit operation. 17.5 automatic clock stretch in the slave modes, the mo dule can synchronize buffer reads and write to the master device by clock stretching. 17.5.1 transmit clock stretching both 10-bit and 7-bit transmit modes implement clock stretching by asserting the sclrel bit after the falling edge of the ninth clock if the tbf bit is cleared, indicat- ing the buffer is empty. in slave transmit modes, clock stretching is always performed, irrespective of the stren bit. clock synchronization takes place following the ninth clock of the transmit sequence. if the device samples an ack on the falling edge of the ninth clock, and if the tbf bit is still clear, then th e sclrel bit is automati- cally cleared. the sclrel being cleared to ? 0 ? will assert the scl line low. the user?s isr must set the sclrel bit before transmission is allowed to con- tinue. by holding the scl line low, the user has time to service the isr and load the contents of the i2ctrn before the master device can initiate another transmit sequence. 17.5.2 receive clock stretching the stren bit in the i2ccon register can be used to enable clock stretching in slave receive mode. when the stren bit is set, the sc l pin will be held low at the end of each data receive sequence. 17.5.3 clock stretching during 7-bit addressing (stren = 1 ) when the stren bit is set in slave receive mode, the scl line is held low when the buffer register is full. the method for stretching the scl output is the same for both 7 and 10-bit addressing modes. clock stretching takes place following the ninth clock of the receive sequence. on th e falling edge of the ninth clock at the end of the ack sequence, if the rbf bit is set, the sclrel bit is automatically cleared, forcing the scl output to be held low. the user?s isr must set the sclrel bit before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the i2crcv before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring. 17.5.4 clock stretching during 10-bit addressing (stren = 1 ) clock stretching takes pl ace automatically during the addressing sequence. beca use this module has a register for the entire addre ss, it is not necessary for the protocol to wait for the address to be updated. after the address phase is complete, clock stretching will occur on each data receive or transmit sequence as was described earlier. 17.6 software controlled clock stretching (stren = 1 ) when the stren bit is ? 1 ?, the sclrel bit may be cleared by software to allow software to control the clock stretching. the logic will synchronize writes to the sclrel bit with the scl clock. clearing the sclrel bit will not assert the scl output until the module detects a falling edg e on the scl output and scl is sampled low. if th e sclrel bit is cleared by the user while the scl line has been sampled low, the scl output will be assert ed (held low). the scl out- put will remain low until the sclrel bit is set, and all other devices on the i 2 c bus have de-asserted scl. this ensures that a write to the sclrel bit will not violate the minimum high time requirement for scl. if the stren bit is ? 0 ?, a software write to the sclrel bit will be disregarded and have no effect on the sclrel bit. note 1: if the user loads the contents of i2ctrn, setting the tbf bit be fore the falling edge of the ninth clock, the sclrel bit will not be cleared and clock stretching will not occur. 2: the sclrel bit can be set in software, regardless of the state of the tbf bit. note 1: if the user reads the contents of the i2crcv, clearing the rbf bit before the falling edge of the ninth clock, the sclrel bit will not be cleared and clock stretching will not occur. 2: the sclrel bit can be set in software, regardless of the state of the rbf bit. the user should be careful to clear the rbf bit in the isr before the next receive sequence in order to prevent an overflow condition.
? 2005 microchip technology inc. preliminary ds70135c-page 109 DSPIC30F4011/4012 17.7 interrupts the i 2 c module generates two interrupt flags, mi2cif (i 2 c master interrupt flag) and si2cif (i 2 c slave inter- rupt flag). the mi2cif inte rrupt flag is activated on completion of a master message event. the si2cif interrupt flag is activated on detection of a message directed to the slave. 17.8 slope control the i 2 c standard requires slope control on the sda and scl signals for fast mode (400 khz). the control bit, disslw, enables the user to disable slew rate con- trol, if desired. it is necess ary to disable the slew rate control for 1 mhz mode. 17.9 ipmi support the control bit ipmien enabl es the module to support intelligent peripheral mana gement interface (ipmi). when this bit is set, the mo dule accepts and acts upon all addresses. 17.10 general call address support the general call address can address all devices. when this address is used, all devices should, in the- ory, respond with an acknowledgement. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all 0 ?s with r_w = 0 . the general call address is recognized when the gen- eral call enable (gcen) bit is set (i2ccon<15> = 1 ). following a start bit detecti on, 8 bits are shifted into i2crsr and the address is compared with i2cadd, and is also compared with the general call address which is fixed in hardware. if a general call address match occurs, the i2crsr is transferred to the i2crcv af ter the eighth clock, the rbf flag is set, and on the falling edge of the ninth bit (ack bit), the master event interrupt flag (mi2cif) is set. when the interrupt is servic ed, the source for the inter- rupt can be checked by reading the contents of the i2crcv to determine if the address was device specific, or a general call address. 17.11 i 2 c master support as a master device, six op erations are supported. assert a start condition on sda and scl. assert a restart condition on sda and scl. write to the i2ctrn register initiating transmission of data/address. generate a stop condition on sda and scl. configure the i 2 c port to receive data. generate an ack condition at the end of a received byte of data. 17.12 i 2 c master operation the master device generate s all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeat ed start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mo de, serial data is output through sda, while scl outp uts the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) a nd the data direction bit. in this case, the data direct ion bit (r_w) is logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmitted, an ack bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. in this case, the data direction bit (r_w) is logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address, followed by a ? 1 ? to indicate receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an ack bit is transmitted. start and stop conditions indicate the beginning and end of transmission. 17.12.1 i 2 c master transmission transmission of a data byte, a 7-bit address, or the sec- ond half of a 10-bit addres s is accomplished by simply writing a value to i2ctrn register. the user should only write to i2ctrn when the module is in a wait state. this action will set the buffer full flag (tbf) and allow the baud rate generat or to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. the transmit status flag, trstat (i2cstat<14>), indicates that a master transmit is in progress.
DSPIC30F4011/4012 ds70135c-page 110 preliminary ? 2005 microchip technology inc. 17.12.2 i 2 c master reception master mode reception is enabled by programming the receive enable (rcen) bit (i2ccon<11>). the i 2 c module must be idle before the rcen bit is set, other- wise the rcen bit wi ll be disregarded. the baud rate generator begins counting, and on each rollover, the state of the scl pin toggles, and data is shifted in to the i2crsr on the rising edge of each clock. 17.12.3 baud rate generator in i 2 c master mode, the rel oad value for the brg is located in the i2cbrg register. when the brg is loaded with this value, t he brg counts down to ? 0 ? and stops until another reload has taken place. if clock arbi- tration is taking place, for in stance, the br g is reloaded when the scl pin is sampled high. as per the i 2 c standard, fsck may be 100 khz or 400 khz. however, the user can specify any baud rate up to 1 mhz. i2cbrg values of ? 0 ? or ? 1 ? are illegal. equation 17-1: i2cbrg value 17.12.4 clock arbitration clock arbitration occurs wh en the master de-asserts the scl pin (scl allowed to float high) during any receive, transmit, or restart/stop condition. when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from count ing until the scl pin is actually sampled high. w hen the scl pin is sampled high, the baud rate generato r is reloaded with the con- tents of i2cbrg and begin s counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device. 17.12.5 multi-master communication, bus collision and bus arbitration multi-master operation support is achieved by bus arbitration. when the mast er outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda, by letting sda float high while another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the mi2cif pulse and reset the master portion of the i 2 c port to its idle state. if a transmit was in progress when the bus collision occurred, the transmission is halted, the tbf flag is cleared, the sda and scl li nes are de-asserted, and a value can now be written to i2ctrn. when the user services the i 2 c master event interrupt service routine, if the i 2 c bus is free (i.e., the p bit is set) the user can resume communicati on by asserting a start condition. if a start, restart, stop or acknowledge condition was in progress when the bus collision occurred, the condi- tion is aborted, the sda and scl lines are de-asserted, and the respective control bits in the i2ccon register are cleared to ? 0 ?. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins, and if a stop condition occurs, the mi2cif bit will be set. a write to the i2ctrn will st art the transmission of data at the first data bit, regard less of where the transmitter left off when bus collision occurred. in a multi-master environment, the interrupt generation on the detection of start and stop conditions allows the determination of when the bu s is free. control of the i 2 c bus can be taken when the p bit is set in the i2cstat register, or the bus is idle and the s and p bits are cleared. 17.13 i 2 c module operation during cpu sleep and idle modes 17.13.1 i 2 c operation during cpu sleep mode when the device enters sl eep mode, all clock sources to the module are shutdown and stay at logic ? 0 ?. if sleep occurs in the middle of a transmission, and the state machine is partially into a transmission as the clocks stop, then the transmission is aborted. similarly, if sleep occurs in the middle of a reception, then the reception is aborted. 17.13.2 i 2 c operation during cpu idle mode for the i 2 c, the i2csidl bit selects if the module will stop on idle or continue on idle. if i2csidl = 0 , the module will continue operation on assertion of the idle mode. if i2csidl = 1 , the module will stop on idle. i2cbrg = f cy f cy f scl 1,111,111 ? 1 ? ()
? 2005 microchip technology inc. preliminary ds70135c-page 111 DSPIC30F4011/4012 table 17-2: i 2 c register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state i2crcv 0200 ? ? ? ? ? ? ? ? receive register 0000 0000 0000 0000 i2ctrn 0202 ? ? ? ? ? ? ? ? transmit register 0000 0000 1111 1111 i2cbrg 0204 ? ? ? ? ? ? ? baud rate generator 0000 0000 0000 0000 i2ccon 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 0001 0000 0000 0000 i2cstat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 0000 0000 0000 i2cadd 020a ? ? ? ? ? ? address register 0000 0000 0000 0000 legend: u = uninitialized bit
DSPIC30F4011/4012 ds70135c-page 112 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 113 DSPIC30F4011/4012 18.0 universal asynchronous receiver transmitter (uart) module this section describes th e universal asynchronous receiver/transmitter communications module. 18.1 uart module overview the key features of the uart module are: full-duplex, 8 or 9-bit data communication even, odd or no parity options (for 8-bit data) one or two stop bits fully integrated baud rate generator with 16-bit prescaler baud rates range from 38 bps to 1.875 mbps at a 30 mhz instruction rate 4-word deep transmit data buffer 4-word deep receive data buffer parity, framing and buffer overrun error detection support for interrupt on ly on address detect (9th bit = 1 ) separate transmit and receive interrupts loopback mode for diagnostic support figure 18-1: uart transmitter block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). write write utx8 uxtxreg low byte load tsr transmit control ? control tsr ? control buffer ? generate flags ? generate interrupt control and status bits uxtxif data ? 0 ? (start) ? 1 ? (stop) parity parity generator transmit shift register (uxtsr) 16 divider control signals 16x baud clock from baud rate generator internal data bus utxbrk note: x = 1 or 2. uxtx dspic30f4012 only has uart1.
DSPIC30F4011/4012 ds70135c-page 114 preliminary ? 2005 microchip technology inc. figure 18-2: uart receiver block diagram read urx8 uxrxreg low byte load rsr uxmode receive buffer control ? generate flags ? generate interrupt uxrxif uxrx start bit detect receive shift register 16 divider control signals uxsta ? shift data characters read read write write to buffer 8-9 (uxrsr) perr ferr parity check stop bit detect shift clock generation wake logic 16 internal data bus 1 0 lpback from uxtx 16x baud clock from baud rate generator
? 2005 microchip technology inc. preliminary ds70135c-page 115 DSPIC30F4011/4012 18.2 enabling and setting up uart 18.2.1 enabling the uart the uart module is enabled by setting the uarten bit in the uxmode register (where x = 1 or 2). once enabled, the uxtx and uxrx pins are configured as an output and an input respec tively, overriding the tris and latch register bit se ttings for the corresponding i/o port pins. the uxtx pin is at logic ? 1 ? when no transmission is taking place. 18.2.2 disabling the uart the uart module is disabled by clearing the uarten bit in the uxmode register. this is the default state after any rese t. if the uart is disabled, all i/o pins operate as port pins under the control of the latch and tris bits of the corresponding port pins. disabling the uart modul e resets the buffers to empty states. any data characters in the buffers are lost, and the baud ra te counter is reset. all error and status flags associated with the uart module are reset when th e module is disabled. the urxda, oerr, ferr, perr, utxen, utxbrk and utxbf bits are cleared, whereas ridle and trmt are set. other control bits, including adden, urxisel<1:0>, utxisel, as well as the uxmode and uxbrg registers, are not affected. clearing the uarten bit whil e the uart is active will abort all pending transmissio ns and receptions and reset the module as defin ed above. re-enabling the uart will restart the uart in the same configuration. 18.2.3 alternate i/o the alternate i/o function is enabled by setting the altio bit (uxmode<10>). if altio = 1 , the uxatx and uxarx pins (alternate transmit and alternate receive pins, respectively) are used by the uart mod- ule instead of the uxtx and uxrx pins. if altio = 0 , the uxtx and uxrx pins are used by the uart module. 18.2.4 setting up data, parity and stop bit selections control bits pdsel<1:0> in the uxmode register are used to select the data length and parity used in the transmission. the data length may either be 8-bits with even, odd or no parity, or 9-bits with no parity. the stsel bit determines whether one or two stop bits will be used during data transmission. the default (power-on) setting of the uart is 8 bits, no parity, 1 stop bit (typically represented as 8, n, 1). 18.3 transmitting data 18.3.1 transmitting in 8-bit data mode the following steps must be performed in order to transmit 8-bit data: 1. set up the uart: first, the data length, parity and number of stop bits must be selected. then, the transmit and receive interrupt enable and priority bits are setup in the uxmode and uxsta registers. also, the appropriate baud rate value must be written to the uxbrg register. 2. enable the uart by setting the uarten bit (uxmode<15>). 3. set the utxen bit (uxsta<10>), thereby enabling a transmission. 4. write the byte to be transmitted to the lower byte of uxtxreg. the value wi ll be transferred to the transmit shift register (uxtsr) immediately and the serial bit stream will start shifting out during the next rising e dge of the baud clock. alternatively, the data byte may be written while utxen = 0 , following which, the user may set utxen. this will cause the serial bit stream to begin immediately becaus e the baud clock will start from a cleared state. 5. a transmit interrupt wi ll be generated depend- ing on the value of the interrupt control bit utxisel (uxsta<15>). 18.3.2 transmitting in 9-bit data mode the sequence of steps involved in the transmission of 9-bit data is similar to 8-bi t transmission, except that a 16-bit data word (of which the upper 7 bits are always clear) must be written to the uxtxreg register. 18.3.3 transmit buffer (u x txb) the transmit buffer is 9-bits wide and 4 characters deep. including the transmit shift register (uxtsr), the user effectively has a 5-deep fifo (first in first out) buffer. the utxbf status bit (uxsta<9>) indicates whether the transmit buffer is full. if a user attempts to write to a full buffer, the new data will not be accepted into the fifo, and no data shift will occur within the buffer. this enables recovery from a buffer overrun condition. the fifo is reset during any device reset, but is not affected when the device enters or wakes up from a power saving mode.
DSPIC30F4011/4012 ds70135c-page 116 preliminary ? 2005 microchip technology inc. 18.3.4 transmit interrupt the transmit interrupt fl ag (u1txif or u2txif) is located in the corresponding interrupt flag register. the transmitter generates an edge to set the uxtxif bit. the condition for gener ating the interrupt depends on utxisel control bit: a) if utxisel = 0 , an interrupt is generated when a word is transferred from the transmit buffer to the transmit shift register (uxtsr). this implies that the transmit buffer has at least one empty word. b) if utxisel = 1 , an interrupt is generated when a word is transferred from the transmit buffer to the transmit shift register (uxtsr) and the transmit buffer is empty. switching between the tw o interrupt modes during operation is possible and sometimes offers more flexibility. 18.3.5 transmit break setting the utxbrk bit (u xsta<11>) will cause the uxtx line to be driven to logic ? 0 ?. the utxbrk bit overrides all transmission activity. therefore, the user should generally wait for the transmitter to be idle before setting utxbrk. to send a break character, the utxbrk bit must be set by software and must remain set for a minimum of 13 baud clock cycles. the utxbrk bit is then cleared by software to g enerate stop bits. th e user must wait for a duration of at least one or two baud clock cycles in order to ensure a valid st op bit(s) before reloading the uxtxb or starting other transmitter activity. trans- mission of a break charac ter does not generate a transmit interrupt. 18.4 receiving data 18.4.1 receiving in 8-bit or 9-bit data mode the following steps must be performed while receiving 8-bit or 9-bit data: 1. set up the uart (see section 18.3.1). 2. enable the uart (see section 18.3.1). 3. a receive interrupt will be generated when one or more data words have been received, depending on the receive interrupt settings specified by the urxisel bits (uxsta<7:6>). 4. read the oerr bit to determine if an overrun error has occurred. the oerr bit must be reset in software. 5. read the received data from uxrxreg. the act of reading uxrxreg will move the next word to the top of the receive fifo, and the perr and ferr values will be updated. 18.4.2 receive buffer (u x rxb) the receive buffer is 4 wo rds deep. including the receive shift register (uxrsr), the user effectively has a 5-word deep fifo buffer. urxda (uxsta<0>) = 1 indicates that the receive buffer has data available. urxda = 0 implies that the buffer is empty. if a user attempts to read an empty buffer, the old values in th e buffer will be read and no data shift will occur within the fifo. the fifo is reset during any device reset. it is not affected when the device enters or wakes up from a power saving mode. 18.4.3 receive interrupt the receive interrupt flag (u1rxif or u2rxif) can be read from the corresponding interrupt flag register. the interrupt flag is set by an edge generated by the receiver. the condition for setting the receive interrupt flag depends on the settings specified by the urxisel<1:0> (uxsta<7:6>) control bits. a) if urxisel<1:0> = 00 or 01 , an interrupt is generated every time a da ta word is transferred from the receive shift register (uxrsr) to the receive buffer. there may be one or more characters in the receive buffer. b) if urxisel<1:0> = 10 , an interrupt is generated when a word is transferred from the receive shift register (uxrsr) to the receive buffer, which, as a result of the transfer, contains 3 characters. c) if urxisel<1:0> = 11 , an interrupt is set when a word is transferred from the receive shift register (uxrsr) to the receive buffer, which, as a result of the transf er, contains 4 characters (i.e., becomes full). switching between the interrupt modes during opera- tion is possible, though g enerally not ad visable during normal operation. 18.5 reception error handling 18.5.1 receive buffer overrun error (oerr bit) the oerr bit (uxsta<1>) is set if all of the following conditions occur: a) the receive buffer is full. b) the receive shift register is full, but unable to transfer the character to the receive buffer. c) the stop bit of the character in the uxrsr is detected, indicating t hat the uxrsr needs to transfer the character to the buffer. once oerr is set, no further data is shifted in uxrsr (until the oerr bit is cleared in software or a reset occurs). the data held in uxrsr and uxrxreg remains valid.
? 2005 microchip technology inc. preliminary ds70135c-page 117 DSPIC30F4011/4012 18.5.2 framing error (ferr) the ferr bit (uxsta<2>) is set if a ? 0 ? is detected instead of a stop bit. if two stop bits are selected, both stop bits must be ? 1 ?, otherwise ferr will be set. the read only ferr bit is buffere d along with the received data. it is cleared on any reset. 18.5.3 parity error (perr) the perr bit (uxsta<3>) is set if the parity of the received word is incorrect. this error bit is applicable only if a parity mode (odd or even) is selected. the read only perr bit is buffere d along with the received data bytes. it is cleared on any reset. 18.5.4 idle status when the receiver is active (i.e., between the initial detection of the start bit and the completion of the stop bit), the ridle bit (uxsta<4>) is ? 0 ?. between the completion of the stop bi t and detection of the next start bit, the ridle bit is ? 1 ?, indicating that the uart is idle. 18.5.5 receive break the receiver will count and expect a certain number of bit times based on the va lues programmed in the pdsel (uxmode<2:1>) and stsel (uxmode<0>) bits. if the break is longer than 13 bit times, the reception is considered complete afte r the number of bit times specified by pdsel and stsel. the urxda bit is set, ferr is set, zeros ar e loaded into the receive fifo, interrupts are generate d, if appropriate and the ridle bit is set. when the module receives a long break signal and the receiver has detected the start bit, the data bits and the invalid stop bit (which sets the ferr), the receiver must wait for a valid stop bit before looking for the next start bit. it cannot assume that the break condition on the line is the next start bit. break is regarded as a character containing all 0 ?s, with the ferr bit set. the break character is loaded into the buffer. no further reception can occur until a stop bit is received. note that ridle goes high when the stop bit has not been received yet. 18.6 address detect mode setting the adden bit (uxsta<5>) enables this special mode, in which a 9t h bit (urx8) value of ? 1 ? identifies the received word as an address rather than data. this mode is only app licable for 9-bit data com- munication. the urxisel co ntrol bit does not have any impact on interrupt g eneration in this mode, since an interrupt (if enabled) will be generated every time the received word has the 9th bit set. 18.7 loopback mode setting the lpback bit enables this special mode in which the uxtx pin is intern ally connected to the uxrx pin. when configured for th e loopback mode, the uxrx pin is disconnected from t he internal uart receive logic. however, the uxtx pi n still functions as in a normal operation. to select this mode: a) configure uart for de sired mode of operation. b) set lpback = 1 to enable loopback mode. c) enable transmission as defined in section 18.3. 18.8 baud rate generator the uart has a 16-bit baud rate generator to allow maximum flexibility in baud rate generation. the baud rate generator register (uxbrg) is readable and writable. the baud rate is computed as follows: brg = 16-bit value held in uxbrg register (0 through 65535) f cy = instruction clock rate (1/t cy ) the baud rate is given by equation 18-1. equation 18-1: baud rate therefore, maximum baud rate possible is f cy /16 (if brg = 0 ), and the minimum baud rate possible is f cy / (16* 65536). with a full 16-bit baud ra te generator, at 30 mips operation, the minimum baud rate achievable is 28.5 bps. baud rate = f cy / (16*(brg+1))
DSPIC30F4011/4012 ds70135c-page 118 preliminary ? 2005 microchip technology inc. 18.9 auto baud support to allow the system to determine baud rates of received characters, the i nput can be optionally linked to a selected capture input (ic1 for uart1, ic2 for uart2). to enable this mode, the user must program the input capture module to detect the falling and rising edges of the start bit. 18.10 uart operation during cpu sleep and idle modes 18.10.1 uart operation during cpu sleep mode when the device enters sleep mode, all clock sources to the module are shutdown and stay at logic ? 0 ?. if entry into sleep mode occurs while a transmission is in progress, then the transmission is aborted. the uxtx pin is driven to logic ? 1 ?. similarly, if entry into sleep mode occurs while a reception is in progress, then the reception is abor ted. the uxsta, uxmode, transmit and receive regist ers and buffers, and the uxbrg register are not affected by sleep mode. if the wake bit (uxmode<7> ) is set before the device enters sleep mode, then a falling edge on the uxrx pin will generate a rece ive interrupt. the receive interrupt select mode bit ( urxisel) has no effect for this function. if the receive interrupt is enabled, then this will wake-up the device from sleep. the uarten bit must be set in orde r to generate a wake-up interrupt. 18.10.2 uart operation during cpu idle mode for the uart, the usidl bit selects if the module will stop operation when the de vice enters idle mode, or whether the module will continue on idle. if usidl = 0 , the module will continue opera tion during idle mode. if usidl = 1 , the module will stop on idle.
? 2005 microchip technology inc. preliminary ds70135c-page 119 DSPIC30F4011/4012 table 18-1: uart1 register map table 18-2: uart2 register map (not available on dspic30f4012) note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state u1mode 020c uarten ?usidl ? ?altio ? ? wake lpback abaud ? ? pdsel1 pdsel0 stsel 0000 0000 0000 0000 u1sta 020e utxisel ? ? ? utxbrk utxen utxbf trmt urxisel1 urxis el0 adden ridle perr ferr oerr urxda 0000 0001 0001 0000 u1txreg 0210 ? ? ? ? ? ? ? utx8 transmit register 0000 000u uuuu uuuu u1rxreg 0212 ? ? ? ? ? ? ? urx8 receive register 0000 0000 0000 0000 u1brg 0214 baud rate generator prescaler 0000 0000 0000 0000 legend: u = uninitialized bit sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state u2mode 0216 uarten ?usidl ? ? ? ? ? wake lpback abaud ? ? pdsel1 pdsel0 stsel 0000 0000 0000 0000 u2sta 0218 utxisel ? ? ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0000 0001 0001 0000 u2txreg 021a ? ? ? ? ? ? ? utx8 transmit register 0000 000u uuuu uuuu u2rxreg 021c ? ? ? ? ? ? ? urx8 receive register 0000 0000 0000 0000 u2brg 021e baud rate generator prescaler 0000 0000 0000 0000 legend: u = uninitialized bit
DSPIC30F4011/4012 ds70135c-page 120 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 121 DSPIC30F4011/4012 19.0 can module 19.1 overview the controller area network (can) module is a serial interface, useful for communicating with other can modules or microcontroller devices. this interface/ protocol was designed to allow communications within noisy environments. the DSPIC30F4011/4012 have 1 can module. the can module is a communi cation controller imple- menting the can 2.0 a/b protocol, as defined in the bosch specification. the module will support can 1.2, can 2.0a, can2.0b passive and can 2.0b active versions of the protocol. the module implemen- tation is a full can system. the can specification is not covered within this data sheet. the reader may refer to the bosch can specification for further details. the module features are as follows: implementation of the can protocol can 1.2, can 2.0a and can 2.0b standard and extended data frames 0-8 bytes data length programmable bit rate up to 1 mbit/sec support for remote frames double buffered receiver with two prioritized received message storage buffers (each buffer may contain up to 8 bytes of data) 6 full (standard/extend ed identifier) acceptance filters, 2 associated with the high priority receive buffer, and 4 associated with the low priority receive buffer 2 full acceptance filter masks, one each associ- ated with the high and low priority receive buffers three transmit buffers with application specified prioritization and abort capability (each buffer may contain up to 8 bytes of data) programmable wake-up functionality with integrated low pass filter programmable loopback mode supports self-test operation signaling via interrupt capabilities for all can receiver and transmitter error states programmable clock source programmable link to input capture module (ic2, for both can1 and can2) for time-stamping and network synchronization low power sleep and idle mode the can bus module consists of a protocol engine, and message buffering/control. the can protocol engine handles all functions for receiving and transmit- ting messages on the can bus. messages are trans- mitted by first loading the appropriate data registers. status and errors can be checked by reading the appropriate registers. any message detected on the can bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers. 19.2 frame types the can module transmits various types of frames, which include data messages or remote transmission requests initiated by the user as other frames that are automatically generated for control purposes. the following frame types are supported: standard data frame a standard data frame is generated by a node when the node wishes to transmit data. it includes a 11-bit standard identifier (sid) but not an 18-bit extended identifier (eid). extended data frame an extended data frame is similar to a standard data frame, but includes an extended identifier as well. remote frame it is possible for a destinatio n node to request the data from the source. for this purpose, the destination node sends a remote frame with an identifier that matches the identifier of the requir ed data frame. the appropri- ate data source node will then send a data frame as a response to this remote request. error frame an error frame is generated by any node that detects a bus error. an error frame consists of 2 fields: an error flag field and an error delimiter field. overload frame an overload frame can be generated by a node as a result of 2 conditions. firs t, the node detects a domi- nant bit during lnterframe space which is an illegal condition. second, due to in ternal conditions, the node is not yet able to start reception of the next message. a node may generate a maximum of 2 sequential overload frames to delay the start of the next message. interframe space interframe space separates a proceeding frame (of whatever type) from a following data or remote frame. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046).
DSPIC30F4011/4012 ds70135c-page 122 preliminary ? 2005 microchip technology inc. figure 19-1: can buffers and protocol engine block diagram acceptance filter rxf2 r x b 1 a c c e p t a c c e p t identifier data field data field identifier acceptance mask rxm1 acceptance filter rxf3 acceptance filter rxf4 acceptance filter rxf5 m a b acceptance mask rxm0 acceptance filter rxf0 acceptance filter rxf1 r x b 0 msgreq txb2 txabt txlarb txerr mtxbuff message message queue control transmit byte sequencer msgreq txb1 txabt txlarb txerr mtxbuff message msgreq txb0 txabt txlarb txerr mtxbuff message receive shift transmit shift receive error transmit error protocol rerrcnt terrcnt errpas busoff finite state machine counter counter transmit logic bit timing logic c1tx c1rx bit timing generator protocol engine buffers crc check crc generator
? 2005 microchip technology inc. preliminary ds70135c-page 123 DSPIC30F4011/4012 19.3 modes of operation the can module can operate in one of several opera- tion modes selected by the user. these modes include: initialization mode disable mode normal operation mode listen only mode loop back mode error recognition mode modes are requested by setting the reqop<2:0> bits (c1ctrl<10:8>), except the error recognition mode which is requested through the rxm<1:0> bits (c1rxncon<6:5>, where n = 0 or 1 represents a particular receive buffer). entry into a mode is acknowledged by monitoring the opmode<2:0> bits (c1ctrl<7:5>). the module will not change the mode and the opmode bits until a change in mode is acceptable, generally durin g bus idle time which is defined as at least 11 c onsecutive recessive bits. 19.3.1 initialization mode in the initialization mode, th e module will not transmit or receive. the error counters are cleared and the inter- rupt flags remain unch anged. the programmer will have access to configuratio n registers that are access restricted in other modes. the module will protect the user from accidentally vi olating the can protocol through programming errors. all registers which control the configuration of the module can not be modified while the module is on-line. the can module will not be allowed to enter the configuration mode while a transmission is taking place. the configuration mode serves as a lock to prot ect the following registers. all module control registers baud rate and interrupt configuration registers bus timing registers identifier acceptance filter registers identifier acceptance mask registers 19.3.2 disable mode in disable mode, the module will not transmit or receive. the module has the ability to set the wakif bit due to bus activity, however any pending interrupts will remain and the error counter s will retain their value. if the reqop<2:0> bits (c1ctrl<10:8>) = ? 001 ?, the module will enter the modul e disable mode. if the mod- ule is active, the module will wait for 11 recessive bits on the can bus, detect that condition as an idle bus, then accept the module d isable command. when the opmode<2:0> bits (c1ctrl<7:5>) = ? 001 ?, that indi- cates whether the module successfully went into mod- ule disable mode. the i/o pins will revert to normal i/o function when the module is in the module disable mode. the module can be program med to apply a low-pass filter function to the c1rx input line while the module or the cpu is in sleep mode. the wakfil bit (c1cfg2<14>) enables or disables the filter. 19.3.3 normal operation mode normal operating mode is selected when reqop<2:0> = ? 000 ?. in this mode, the module is activated, the i/o pins will assume the can bus functions. the module will transmit and receive can bus messages via the c1tx and c1rx pins. 19.3.4 listen only mode if the listen only mode is activated, the module on the can bus is passive. the transmitter buffers revert to the port i/o function. the receive pins remain inputs. for the receiver, no error flags or acknowledge signals are sent. the error counter s are deactivated in this state. the listen only mode can be used for detecting the baud rate on the can bus. to use this, it is neces- sary that there are at l east two further nodes that communicate with each other. 19.3.5 error recognition mode the module can be set to ignore all errors and receive any message. the error reco gnition mode is activated by setting the rxm<1:0> bits (c1rxncon<6:5>) reg- isters to ? 11 ?. in this mode the data which is in the message assembly buffer until the time an error occurred, is copied in th e receive buffer and can be read via the cpu interface. 19.3.6 loop back mode if the loopback mode is activa ted, the module will con- nect the internal transmit sig nal to the internal receive signal at the module bo undary. the transmit and receive pins revert to their port i/o function. note: typically, if the can module is allowed to transmit in a particular mode of operation and a transmission is requested immedi- ately after the can module has been placed in that mode of operation, the mod- ule waits for 11 consecutive recessive bits on the bus before starting transmission. if the user switches to disable mode within this 11-bit period, then this transmission is aborted and the corr esponding txabt bit is set and txreq bit is cleared.
DSPIC30F4011/4012 ds70135c-page 124 preliminary ? 2005 microchip technology inc. 19.4 message reception 19.4.1 receive buffers the can bus module has 3 receive buffers. however, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. this buffer is called the message assembly buffer (mab). so there are 2 receive buffers visible, rxb0 and rxb1, that can essentially instantaneously receive a complete message from the protocol engine. all messages are assembled by the mab, and are transferred to the rxbn buffers only if the acceptance filter criterion are met. when a message is received, the rxnif flag (c1intf<0> or c1inrf<1>) will be set. this bit can only be set by the module when a message is received. the bit is clear ed by the cpu when it has completed processing the me ssage in the buffer. if the rxnie bit (c1inte<0> or c1inte<1>) is set, an inter- rupt will be generated when a message is received. rxf0 and rxf1 filters with rxm0 mask are associated with rxb0. the filters rxf2, rxf3, rxf4, and rxf5 and the mask rxm1 are associated with rxb1. 19.4.2 message acceptance filters the message acceptance filt ers and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buff- ers. once a valid message has been received into the message assembly buffer (mab), the identifier fields of the message are compared to the filter values. if there is a match, that message will be loaded into the appropriate receive buffer. the acceptance filter looks at incoming messages for the rxide bit (cirxnsid< 0>) to determine how to compare the identifiers. if the rxide bit is clear, the message is a standard frame, and only filters with the exide bit (c1rxfnsid<0>) clear are compared. if the rxide bit is set, the messag e is an extended frame, and only filters with the exide bit set are compared. configuring the rxm<1:0> bits to 01 or 10 can override the exide bit. 19.4.3 message acceptance filter masks the mask bits essentially determine which bits to apply the filter to. if any mask bit is set to a zero, then that bit will automatically be accepted regardless of the filter bit. there are 2 programmable acceptance filter masks associated with the receive buffers, one for each buffer. 19.4.4 receive overrun an overrun condition oc curs when the message assembly buffer (mab) has assembled a valid received message, the message is accepted through the acceptance filters, and when the receive buffer associated with the filter has not been designated as clear of the previous message. the overrun error flag, rxnovr (c1intf<15> or c1intf<14>) and the errif bit (c1intf<5>) will be set and the message in th e mab will be discarded. if the dben bit is clear, r xb1 and rxb0 operate inde- pendently. when this is the case, a message intended for rxb0 will not be dive rted into rxb1 if rxb0 contains an unread messag e and the rx0ovr bit will be set. if the dben bit is set, the overrun for rxb0 is handled differently. if a valid messag e is received for rxb0 and rxful = 1 indicates that rxb0 is full, and rxful = 0 indicates that rxb1 is em pty, the message for rxb0 will be loaded into rxb1. an overrun error will not be generated for rxb0. if a va lid message is received for rxb0 and rxful = 1 , and rxful = 1 indicating that both rxb0 and rxb1 are full , the message will be lost and an overrun will be indicated for rxb1. 19.4.5 receive errors the can module will detect the following receive errors: cyclic redundancy check (crc) error bit stuffing error invalid message receive error these receive errors do not generate an interrupt. however, the receive error counter is incremented by one in case one of these er rors occur. the rxwar bit (c1intf<9>) indicates that the receive error counter has reached the cpu warning limit of 96 and an interrupt is generated. 19.4.6 receive interrupts receive interrupts can be divided into 3 major groups, each including various cond itions that generate interrupts: receive interrupt a message has been successfully received and loaded into one of the receive buff ers. this interrupt is acti- vated immediately after receiving the end-of-frame (eof) field. reading the rx nif flag will indicate which receive buffer caused the interrupt. wake-up interrupt the can module has woken up from disable mode or the device has woken up from sleep mode.
? 2005 microchip technology inc. preliminary ds70135c-page 125 DSPIC30F4011/4012 receive error interrupts a receive error interrupt will be indicated by the errif bit. this bit shows that an error condition occurred. the source of the error can be determined by checking the bits in the can interrupt status register c1intf. invalid message received if any type of error occurred during reception of the last message, an error will be indicated by the ivrif bit. receiver overrun the rxnovr bit indicates that an overrun condi- tion occurred. receiver warning the rxwar bit indicates that the receive error counter (rerrcnt<7:0>) has reached the warning limit of 96. receiver error passive the rxep bit indicates that the receive error counter has exceeded the error passive limit of 127 and the module has gone into error passive state. 19.5 message transmission 19.5.1 transmit buffers the can module has three transmit buffers. each of the three buffers occupies 14 bytes of data. eight of the bytes are the maximum 8 bytes of the transmitted mes- sage. five bytes hold the standard and extended identifiers and other message arbitration information. 19.5.2 transmit message priority transmit priority is a prioritization within each node of the pending transmittable messages. there are 4 levels of transmit priority. if txpri<1:0> (c1txncon<1:0>, where n = 0 , 1 or 2 represents a particular transmit buffer) for a particular message buffer is set to ? 11 ?, that buffer has the highest priority. if txpri<1:0> for a particular message buffer is set to ? 10 ? or ? 01 ?, that buffer has an intermediate priority. if txpri<1:0> for a particular message buffer is ? 00 ?, that buffer has the lowest priority. 19.5.3 transmission sequence to initiate transmission of the message, the txreq bit (c1txncon<3>) must be set. the can bus module resolves any timing confl icts between setting of the txreq bit and the start of frame (sof), ensuring that if the priority was changed, it is resolved correctly before the sof occurs. when txreq is set, the txabt (c1txncon<6>), txlarb (c1txncon<5>) and txerr (c1txncon<4>) flag bits are automatically cleared. setting txreq bit simply fl ags a message buffer as enqueued for transmission. when the module detects an available bus, it begi ns transmitting the message which has been determined to have the highest priority. if the transmission completes successfully on the first attempt, the txreq bit is cl eared automatically and an interrupt is generated if txie was set. if the message transmission fails, one of the error condition flags will be se t and the txreq bit will remain set indicating that the message is still pending for transmission. if the mess age encountered an error condition during the tran smission attempt, the txerr bit will be set and the er ror condition may cause an interrupt. if the message loses arbitration during the transmission attempt, the txlarb bit is set. no interrupt is generated to si gnal the loss of arbitration. 19.5.4 aborting message transmission the system can also abort a message by clearing the txreq bit associated with each message buffer. set- ting the abat bit (c1ctrl<12>) will request an abort of all pending messages. if the message has not yet started transmission, or if the message started but is interrupted by loss of arbitr ation or an error, the abort will be processed. the abort is indicated when the module sets the txabt bit, and the txnif flag is not automatically set. 19.5.5 transmission errors the can module will detect the following transmission errors: acknowledge error form error bit error these transmission errors wi ll not necessarily generate an interrupt but are indicate d by the transmission error counter. however, each of these errors will cause the transmission error counter to be incremented by one. once the value of the erro r counter exceeds the value of 96, the errif (c1intf<5>) and the txwar bit (c1intf<10>) are set. once the value of the error counter exceeds the value of 96, an interrupt is gener- ated and the txwar bit in the error flag register is set.
DSPIC30F4011/4012 ds70135c-page 126 preliminary ? 2005 microchip technology inc. 19.5.6 transmit interrupts transmit interrupts can be di vided into 2 major groups, each including various c onditions that generate interrupts: transmit interrupt at least one of the three transmit buffers is empty (not scheduled) and can be load ed to schedule a message for transmission. reading the txnif flags will indicate which transmit buffer is available and caused the interrupt. transmit error interrupts a transmission error interrupt will be indicated by the errif flag. this flag shows that an error condition occurred. the source of the error can be determined by checking the error flags in the can interrupt status reg- ister, c1intf. the flags in this register are related to receive and transmit errors. transmitter warning interrupt the txwar bit indicates th at the transmit error counter has reached the cp u warning limit of 96. transmitter error passive the txep bit (c1intf<12>) indicates that the transmit error counter has exceeded the error passive limit of 127 and the module has gone to error passive state. bus off the txbo bit (c1intf<13>) indicates that the transmit error counter has exceeded 255 and the module has gone to bus off state. 19.6 baud rate setting all nodes on any particular can bus must have the same nominal bit rate. in orde r to set the baud rate, the following parameters ha ve to be initialized: synchronization jump width baud rate prescaler phase segments length determination of phase2 seg sample point propagation segment bits 19.6.1 bit timing all controllers on the can bus must have the same baud rate and bit length. howe ver, different controllers are not required to have the same master oscillator clock. at different clock fr equencies of the individual controllers, the baud rate has to be adjusted by adjust- ing the number of time quanta in each segment. the nominal bit time can be thought of as being divided into separate non-ov erlapping time segments. these segments are shown in figure 19-2. synchronization segment (sync seg) propagation time segment (prop seg) phase segment 1 (phase1 seg) phase segment 2 (phase2 seg) the time segments and also the nominal bit time are made up of integer units of time called time quanta or t q . by definition, the nominal bit time has a minimum of 8 t q and a maximum of 25 t q . also, by definition, the minimum nominal bit time is 1 sec, corresponding to a maximum bit rate of 1 mhz. figure 19-2: can bit timing input signal sync prop segment phase segment 1 phase segment 2 sync sample point t q
? 2005 microchip technology inc. preliminary ds70135c-page 127 DSPIC30F4011/4012 19.6.2 prescaler setting there is a programmable prescaler, with integral val- ues ranging from 1 to 64, in addition to a fixed divide- by-2 for clock generati on. the time quantum (t q ) is a fixed unit of time derived fr om the oscillator period, and is given by equation 19-1, where f can is f cy (if the cancks bit is set or 4 f cy (if cancks is cleared). equation 19-1: time quantum for clock generation 19.6.3 propagation segment this part of the bit time is used to compensate physical delay times within the netw ork. these delay times con- sist of the signal propagation time on the bus line and the internal delay time of the nodes. the propagation segment can be programmed from 1 t q to 8 t q by setting the prseg<2:0> bits (c1cfg2<2:0>). 19.6.4 phase segments the phase segments are used to optimally locate the sampling of the received bit within the transmitted bit time. the sampling point is between phase1 seg and phase2 seg. these segments are lengthened or short- ened by re-synchronizati on. the end of the phase1 seg determines the sampling point within a bit period. the segment is programmable from 1 t q to 8 t q . phase2 seg provides delay to the next transmitted data transition. the segment is programmable from 1 t q to 8t q , or it may be defined to be equal to the greater of phase1 seg or the information processing time (2 t q ). the phase1 seg is in itialized by setting bits seg1ph<2:0> (c1cfg2<5:3>), and phase2 seg is initialized by setting seg2ph<2:0> (c1cfg2<10:8>). the following requirement mu st be fulfilled while setting the lengths of the phase segments: propagation segment + phase1 seg > = phase2 seg 19.6.5 sample point the sample point is the poin t of time at which the bus level is read and interpreted as the value of that respec- tive bit. the location is at th e end of phase1 seg. if the bit timing is slow an d contains many t q , it is possible to specify multiple sampling of the bus line at the sample point. the level determined by the can bus then corre- sponds to the result from the majority decision of three values. the majority samples are taken at the sample point and twice before with a distance of t q /2. the can module allows the us er to chose between sam- pling three times at the same point or once at the same point, by setting or clearin g the sam bit (c1cfg2<6>). typically, the sampling of the bit should take place at about 60-70% through the bit time, depending on the system parameters. 19.6.6 synchronization to compensate for phase sh ifts between the oscillator frequencies of the different bus stations, each can controller must be able to synchronize to the relevant signal edge of the incoming signal. when an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (synchro- nous segment). the circuit wi ll then adjust the values of phase1 seg and phas e2 seg. there are 2 mechanisms used to synchronize. 19.6.6.1 hard synchronization hard synchronization is on ly done whenever there is a 'recessive' to 'dominant' edge during bus idle, indicat- ing the start of a message. after hard synchronization, the bit time counters are restarted with the synchro- nous segment. hard synchronization forces the edge which has caused the hard synchronization to lie within the synchronization segment of the restarted bit time. if a hard synchronization is do ne, there will not be a re-synchronization wi thin that bit time. 19.6.6.2 re-synchronization as a result of re-synchr onization, phase1 seg may be lengthened or phase2 seg may be shortened. the amount of lengthening or shortening of the phase buffer segment has an upper bound known as the syn- chronization jump width, and is specified by the sjw<1:0> bits (c1cfg1<7:6> ). the value of the syn- chronization jump width will be added to phase1 seg or subtracted from phase2 se g. the re-synchronization jump width is programmable between 1 t q and 4 t q . the following requirement must be fulfilled while setting the sjw<1:0> bits: phase2 seg > synchronization jump width note: f can must not exceed 30 mhz. if cancks = 0, then f cy must not exceed 7.5 mhz. t q = 2 ( brp<5:0> + 1 ) / f can
DSPIC30F4011/4012 ds70135c-page 128 preliminary ? 2005 microchip technology inc. table 19-1: can1 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state c1rxf0sid 0300 ? ? ? receive acceptance filter 0 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c1rxf0eidh 0302 ? ? ? ? receive acceptance filter 0 extended iden tifier <17:6> 0000 uuuu uuuu uuuu c1rxf0eidl 0304 receive acceptance filter 0 exte nded identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf1sid 0308 ? ? ? receive acceptance filter 1 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c1rxf1eidh 030a ? ? ? ? receive acceptance filter 1 extended iden tifier <17:6> 0000 uuuu uuuu uuuu c1rxf1eidl 030c receive acceptance filter 1 exte nded identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf2sid 0310 ? ? ? receive acceptance filter 2 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c1rxf2eidh 0312 ? ? ? ? receive acceptance filter 2 extended iden tifier <17:6> 0000 uuuu uuuu uuuu c1rxf2eidl 0314 receive acceptance filter 2 exte nded identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf3sid 0318 ? ? ? receive acceptance filter 3 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c1rxf3eidh 031a ? ? ? ? receive acceptance filter 3 extended iden tifier <17:6> 0000 uuuu uuuu uuuu c1rxf3eidl 031c receive acceptance filter 3 exte nded identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf4sid 0320 ? ? ? receive acceptance filter 4 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c1rxf4eidh 0322 ? ? ? ? receive acceptance filter 4 extended iden tifier <17:6> 0000 uuuu uuuu uuuu c1rxf4eidl 0324 receive acceptance filter 4 exte nded identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf5sid 0328 ? ? ? receive acceptance filter 5 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c1rxf5eidh 032a ? ? ? ? receive acceptance filter 5 extended iden tifier <17:6> 0000 uuuu uuuu uuuu c1rxf5eidl 032c receive acceptance filter 5 exte nded identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxm0sid 0330 ? ? ? receive acceptance mask 0 standard identifier <10:0> ? mide 000u uuuu uuuu uu0u c1rxm0eidh 0332 ? ? ? ? receive acceptance mask 0 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxm0eidl 0334 receive acceptance mask 0 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxm1sid 0338 ? ? ? receive acceptance mask 1 standard identifier <10:0> ? mide 000u uuuu uuuu uu0u c1rxm1eidh 033a ? ? ? ? receive acceptance mask 1 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxm1eidl 033c receive acceptance mask 1 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1tx2sid 0340 transmit buffer 2 standard identifier <10:6> ? ? ? transmit buffer 2 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c1tx2eid 0342 transmit buffer 2 extended identifier <17:14> ? ? ? ? transmit buffer 2 ext ended identifier <13:6> uuuu 0000 uuuu uuuu c1tx2dlc 0344 transmit buffer 2 extended identifier <5 :0> txrtr txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 c1tx2b1 0346 transmit buffer 2 by te 1 transmit buffer 2 byte 0 uuuu uuuu uuuu uuuu c1tx2b2 0348 transmit buffer 2 by te 3 transmit buffer 2 byte 2 uuuu uuuu uuuu uuuu c1tx2b3 034a transmit buffer 2 byte 5 transmit buff er 2 byte 4 uuuu uuuu uuuu uuuu c1tx2b4 034c transmit buffer 2 by te 7 transmit buffer 2 byte 6 uuuu uuuu uuuu uuuu c1tx2con 034e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c1tx1sid 0350 transmit buffer 1 standard identifier <10:6> ? ? ? transmit buffer 1 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c1tx1eid 0352 transmit buffer 1 extended identifier <17:14> ? ? ? ? transmit buffer 1 ext ended identifier <13:6> uuuu 0000 uuuu uuuu c1tx1dlc 0354 transmit buffer 1 extended identifier <5 :0> txrtr txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 c1tx1b1 0356 transmit buffer 1 by te 1 transmit buffer 1 byte 0 uuuu uuuu uuuu uuuu legend: u = uninitialized bit
? 2005 microchip technology inc. preliminary ds70135c-page 129 DSPIC30F4011/4012 note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. c1tx1b2 0358 transmit buffer 1 by te 3 transmit buffer 1 byte 2 uuuu uuuu uuuu uuuu c1tx1b3 035a transmit buffer 1 byte 5 transmit buff er 1 byte 4 uuuu uuuu uuuu uuuu c1tx1b4 035c transmit buffer 1 by te 7 transmit buffer 1 byte 6 uuuu uuuu uuuu uuuu c1tx1con 035e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c1tx0sid 0360 transmit buffer 0 standard identifier <10:6> ? ? ? transmit buffer 0 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c1tx0eid 0362 transmit buffer 0 extended identifier <17:14> ? ? ? ? transmit buffer 0 ext ended identifier <13:6> uuuu 0000 uuuu uuuu c1tx0dlc 0364 transmit buffer 0 extended identifier <5 :0> txrtr txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 c1tx0b1 0366 transmit buffer 0 by te 1 transmit buffer 0 byte 0 uuuu uuuu uuuu uuuu c1tx0b2 0368 transmit buffer 0 by te 3 transmit buffer 0 byte 2 uuuu uuuu uuuu uuuu c1tx0b3 036a transmit buffer 0 byte 5 transmit buff er 0 byte 4 uuuu uuuu uuuu uuuu c1tx0b4 036c transmit buffer 0 by te 7 transmit buffer 0 byte 6 uuuu uuuu uuuu uuuu c1tx0con 036e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c1rx1sid 0370 ? ? ? receive buffer 1 standard identifier <10:0> srr rxide 000u uuuu uuuu uuuu c1rx1eid 0372 ? ? ? ? receive buffer 1 exte nded identifier <17:6> 0000 uuuu uuuu uuuu c1rx1dlc 0374 receive buffer 1 ex tended identifier <5:0> rxrtr rxrb1 ? ? ? rxrb0 dlc<3:0> uuuu uuuu 000u uuuu c1rx1b1 0376 receive buffer 1 by te 1 receive buffer 1 byte 0 uuuu uuuu uuuu uuuu c1rx1b2 0378 receive buffer 1 by te 3 receive buffer 1 byte 2 uuuu uuuu uuuu uuuu c1rx1b3 037a receive buffer 1 byte 5 receive buffer 1 byte 4 uuuu uuuu uuuu uuuu c1rx1b4 037c receive buffer 1 by te 7 receive buffer 1 byte 6 uuuu uuuu uuuu uuuu c1rx1con 037e ? ? ? ? ? ? ? ?rxful ? ? ? rxrtrro filhit<2:0> 0000 0000 0000 0000 c1rx0sid 0380 ? ? ? receive buffer 0 standard identifier <10:0> srr rxide 000u uuuu uuuu uuuu c1rx0eid 0382 ? ? ? ? receive buffer 0 exte nded identifier <17:6> 0000 uuuu uuuu uuuu c1rx0dlc 0384 receive buffer 0 ex tended identifier <5:0> rxrtr rxrb1 ? ? ? rxrb0 dlc<3:0> uuuu uuuu 000u uuuu c1rx0b1 0386 receive buffer 0 by te 1 receive buffer 0 byte 0 uuuu uuuu uuuu uuuu c1rx0b2 0388 receive buffer 0 by te 3 receive buffer 0 byte 2 uuuu uuuu uuuu uuuu c1rx0b3 038a receive buffer 0 byte 5 receive buffer 0 byte 4 uuuu uuuu uuuu uuuu c1rx0b4 038c receive buffer 0 by te 7 receive buffer 0 byte 6 uuuu uuuu uuuu uuuu c1rx0con 038e ? ? ? ? ? ? ? ?rxful ? ? ? rxrtrro dben jtoff filhit0 0000 0000 0000 0000 c1ctrl 0390 cancap ? csidle abat cancks reqop<2:0> opmode<2:0> ? icode<2:0> ? 0000 0100 1000 0000 c1cfg1 0392 ? ? ? ? ? ? ? ? sjw<1:0> brp<5:0> 0000 0000 0000 0000 c1cfg2 0394 ? wakfil ? ? ? seg2ph<2:0> seg2phts sam seg1ph<2:0> prseg<2:0> 0u00 0uuu uuuu uuuu c1intf 0396 rx0ovr rx1ovr txbo txep rxep txwar rxwar ew arn ivrif wakif errif tx2if tx1if tx0if rx1if rx0if 0000 0000 0000 0000 c1inte 0398 ? ? ? ? ? ? ? ? ivrie wakie errie tx2ie tx1ie tx0ie rx1e rx0ie 0000 0000 0000 0000 c1ec 039a transmit error count regist er receive error count register 0000 0000 0000 0000 table 19-1: can1 register map (continued) sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state legend: u = uninitialized bit
DSPIC30F4011/4012 ds70135c-page 130 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 131 DSPIC30F4011/4012 20.0 10-bit high speed analog- to-digital converter (a/d) module the10-bit high-speed analog-to -digital converter (a/d) allows conversion of an anal og input signal to a 10-bit digital number. this module is based on a successive approximation register (sar) architecture, and pro- vides a maximum sampling ra te of 500 ksps. the a/d module has 16 an alog inputs which are multiplexed into four sample and hold amplif iers. the output of the sam- ple and hold is the input into the converter, which gen- erates the result. the anal og reference voltages are software selectable to eith er the device supply voltage (av dd /av ss ) or the voltage level on the (v ref +/v ref -) pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. the a/d module has six 16-bit registers: a/d control register1 (adcon1) a/d control register2 (adcon2) a/d control register3 (adcon3) a/d input select register (adchs) a/d port configuration register (adpcfg) a/d input scan select ion register (adcssl) the adcon1, adcon2 and adcon3 registers con- trol the operation of the a/d module. the adchs reg- ister selects the input cha nnels to be converted. the adpcfg register configures the port pins as analog inputs or as digital i/o. the adcssl register selects inputs for scanning. the block diagram of the a/d module is shown in figure 20-1. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: the ssrc<2:0>, asam, simsam, smpi<3:0>, bufm and alts bits, as well as the adcon3 and adcssl registers, must not be written to while adon = 1 . this would lead to indeterminate results.
DSPIC30F4011/4012 ds70135c-page 132 preliminary ? 2005 microchip technology inc. figure 20-1: 10-bit high speed a/d functional block diagram s/h + - 10-bit result conversion logic v ref + av ss av dd adc data 16-word, 10-bit dual port buffer bus interface an0 an5 an7 an1 an2 an3 an4 an6 an8 *an8 an4 an5 *an6 *an7 an0 an1 an2 an3 ch1 ch2 ch3 ch0 an5 an2 an8 an4 an1 an7 an3 an0 an6 an1 v ref - sample/sequence control sample ch1,ch2, ch3,ch0 input mux control input switches s/h + - s/h + - s/h + - format * = not available on dspic30f4012.
? 2005 microchip technology inc. preliminary ds70135c-page 133 DSPIC30F4011/4012 20.1 a/d result buffer the module contains a 16-word dual port read-only buffer, called adcbuf0...adcbuff, to buffer the a/d results. the ram is 10-bits wide, but is read into different format 16-bit words. the contents of the sixteen a/d conversion result buffer re gisters, adcbuf0 through adcbuff, cannot be written by user software. 20.2 conversion operation after the a/d module has been configured, the sample acquisition is started by setting the samp bit. various sources, such as a programmable bit, timer time-outs and external events, will terminate acquisition and start a con- version. when the a/d conversion is complete, the result is loaded into adcbuf0 ...adcbuff, and the a/d interrupt flag adif and the done bit are set after the number of samples specified by the smpi bit. the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: - configure analog pins, voltage reference and digital i/o - select a/d input channels - select a/d conversion clock - select a/d conversion trigger - turn on a/d module 2. configure a/d interrupt (if required): - clear adif bit - select a/d interrupt priority 3. start sampling. 4. wait the required acquisition time. 5. trigger acquisition end, start conversion 6. wait for a/d conversion to complete, by either: - waiting for the a/d interrupt 7. read a/d result buffer , clear adif if required. 20.3 selecting the conversion sequence several groups of control bits select the sequence in which the a/d connects inpu ts to the sample/hold channels, converts channels, writes the buffer memory, and generates interrupts. the sequence is controlled by the sampling clocks. the simsam bit controls the acquire/convert sequence for multiple chan nels. if the simsam bit is ? 0 ?, the two or four selected channels are acquired and converted sequentially, with two or four sample clocks. if the simsam bit is ? 1 ?, two or four selected channels are acquired simultaneously, with one sample clock. the channels are then conv erted sequentially. obvi- ously, if there is only 1 channel selected, the simsam bit is not applicable. the chps bits selects ho w many channels are sam- pled. this can vary from 1, 2 or 4 channels. if chps selects 1 channel, the ch0 c hannel will be sampled at the sample clock and converted. the result is stored in the buffer. if chps selects 2 channels, the ch0 and ch1 channels will be samp led and converted. if chps selects 4 channels, th e ch0, ch1, ch2 and ch3 channels will be samp led and converted. the smpi bits select the nu mber of acquisition/conver- sion sequences that woul d be performed before an interrupt occurs. this can vary from 1 sample per interrupt to 16 samples per interrupt. the user cannot program a combination of chps and smpi bits that specifies more than 16 conversions per interrupt, or 8 conversions per interrupt, depending on the bufm bit. the bufm bit, when set, will split the 16--word results buffer (adcbuf0...adcbuff) into two 8-word groups. writing to the 8-word buffers will be alternated on each interrupt event. use of the bufm bit will depend on how much ti me is available for moving data out of the buffers after the interrupt, as determined by the application. if the processor can quickly un load a full buffer within the time it takes to acqu ire and convert one channel, the bufm bit can be ? 0 ? and up to 16 conversions may be done per interrupt. the processor will have one sample and conversion ti me to move the sixteen conversions. if the processor cannot unlo ad the buffer within the acquisition and conversion time, the bufm bit should be ? 1 ?. for example, if smpi<3:0> (adcon2<5:2>) = 0111 , then eight conversions wi ll be loaded into 1/2 of the buffer, following which an interrupt occurs. the next eight conversions will be load ed into the other 1/2 of the buffer. the processor will have the entire time between interrupts to move the eight conversions. the alts bit can be used to alternate the inputs selected during the samplin g sequence. the input mul- tiplexer has two sets of sample inputs: mux a and mux b. if the alts bit is ? 0 ?, only the mux a inputs are selected for sampling. if the alts bit is ? 1 ? and smpi<3:0> = 0000 , on the first sample/convert sequence, the mux a inputs are selected, and on the next acquire/convert sequence, the mux b inputs are selected. the cscna bit (adcon2<1 0>) will allow the ch0 channel inputs to be alte rnately scanned across a selected number of analog inputs for the mux a group. the inputs are selected by the adcssl register. if a particular bit in the adcssl register is ? 1 ?, the corre- sponding input is selected. the inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. if the num ber of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused.
DSPIC30F4011/4012 ds70135c-page 134 preliminary ? 2005 microchip technology inc. 20.4 programming the start of conversion trigger the conversion trigger will terminate acquisition and start the requested conversions. the ssrc<2:0> bits select the source of the conversion trigger. the ssrc bits provide for up to 5 alternate sources of conversion trigger. when ssrc<2:0> = 000 , the conversion trigger is under software control. cl earing the samp bit will cause the conversion trigger. when ssrc<2:0> = 111 (auto start mode), the con- version trigger is under a/ d clock control. the samc bits select the number of a/d clocks between the start of acquisition and the start of conversion. this provides the fastest conversion rate s on multiple channels. samc must always be at least 1 clock cycle. other trigger sources can come from timer modules, motor control pwm module, or external interrupts. 20.5 aborting a conversion clearing the adon bit duri ng a conversion will abort the current conversion and stop the sampling sequenc- ing. the adcbuf will not be updated with the partially completed a/d conversion sample. that is, the adcbuf will continue to co ntain the value of the last completed conversion (or the last value written to the adcbuf register). if the clearing of the adon bit coincides with an auto start, the clearing has a higher priority. after the a/d conversion is aborted, a 2 t ad wait is required before the next sampling may be started by setting the samp bit. if sequential sampling is specif ied, the a/d will continue at the next sample pulse which corresponds with the next channel converted. if simultaneous sampling is specified, the a/d will continue with the next multi-channel group conversion sequence. 20.6 selecting the a/d conversion clock the a/d conversion requires 12 t ad . the source of the a/d conversion clock is software selected using a six bit counter. there are 64 possible options for t ad . equation 20-1: a/d conversion clock the internal rc oscillator is selected by setting the adrc bit. for correct a/d conversions , the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 154 nsec (for v dd = 5v). refer to the electrical specifications section for minimum t ad under other operating conditions. example 20-1 shows a sample calculation for the adcs<5:0> bits, assuming a device operating speed of 30 mips. example 20-1: a/d conversion clock calculation note: to operate the a/d at the maximum spec- ified conversion speed, the auto convert trigger option should be selected (ssrc = 111 ) and the auto sample time bits shoud be set to 1 t ad (samc = 00001 ). this configuration will give a total conver- sion period (sample + convert) of 13 t ad . the use of any other conversion trigger will result in additional t ad cycles to synchronize the external event to the a/d. t ad = t cy * (0.5*(adcs<5:0> +1)) adcs<5:0> = 2 ? 1 t ad t cy minimum t ad = 154 nsec adcs<5:0> = 2 ? 1 t ad t cy t cy = 33 nsec (30 mips) = 2 ? 1 154 nsec 33 nsec = 8.33 therefore, set adcs<5:0> = 9 actual t ad = (adcs<5:0> + 1) t cy 2 = (9 + 1) 33 nsec 2 = 165 nsec
? 2005 microchip technology inc. preliminary ds70135c-page 135 DSPIC30F4011/4012 20.7 a/d acquisition requirements the analog input model of the 10-bit a/d converter is shown in figure 20-2. the total sampling time for the a/d is a function of the inter nal amplifier settling time, device v dd and the holding capacitor charge time. for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the voltag e level on the analog input pin. the source impedance (r s ), the interconnect impedance (r ic ), and the internal sampling switch (r ss ) impedance combine to directly affect the time required to charge the capacitor c hold . the combined impedance of the analog sources must therefore be small enough to fully charge the holding capacitor within the chosen sample ti me. to minimize the effects of pin leakage currents on the accuracy of the a/d con- verter, the maximum re commended source imped- ance, r s , is 5 k ? . after the analog input channel is selected (changed), this sampling function must be completed prior to starting the conversion. the internal holding capacitor will be in a discharged state prior to each sample operation. the user must allow at least 1 t ad period of sampling time, t samp , between conversions to allow each sam- ple to be acquired. this samp le time may be controlled manually in software by setting/clearing the samp bit, or it may be automatically co ntrolled by the a/d con- verter. in an automatic configuration, the user must allow enough time between conversion triggers so that the minimum sample time can be satisfied. refer to the electrical specifications for t ad and sample time requirements. figure 20-2: a/d converter analog input model c pin va rs anx v t = 0.6v v t = 0.6v i leakage r ic 250 ? sampling switch r ss c hold = dac capacitance v ss v dd = 4.4 pf 500 na legend: c pin v t i leakage r ic r ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch resistance = sample/hold capacitance (from dac) various junctions note: c pin value depends on device package an d is not tested. effect of c pin negligible if rs 5 k ? . r ss 3 k ?
DSPIC30F4011/4012 ds70135c-page 136 preliminary ? 2005 microchip technology inc. 20.8 module power-down modes the module has 3 internal power modes. when the adon bit is ? 1 ?, the module is in active mode; it is fully powered and functional. when adon is ? 0 ?, the module is in off mode. the digital and analog portions of the circuit are disabled for ma ximum current savings. in order to return to the act ive mode from off mode, the user must wait for the adc circuitry to stabilize. 20.9 a/d operation during cpu sleep and idle modes 20.9.1 a/d operation during cpu sleep mode when the device enters sleep mode, all clock sources to the module are shutdown and stay at logic ? 0 ?. if sleep occurs in the middle of a conversion, the con- version is aborted. the converter will not continue with a partially completed conver sion on exit from sleep mode. register contents are not affected by the device entering or leaving sleep mode. the a/d module can operate du ring sleep mode if the a/d clock source is set to rc (adrc = 1 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switch ing noise from the conver- sion. when the conversion is complete, the done bit will be set and the result loaded into the adcbuf register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interr upt is not enabled, the a/d module will then be turned off, although the adon bit will remain set. 20.9.2 a/d operation during cpu idle mode the adsidl bit selects if the module will stop on idle or continue on idle. if adsidl = 0 , the module will con- tinue operation on assertion of idle mode. if adsidl = 1 , the module will stop on idle. 20.10 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion and acquisition sequence is aborted. the values that are in the adcbuf registers are not modi- fied. the a/d result register will contain unknown data after a power-on reset. 20.11 output formats the a/d result is 10-bits wi de. the data buffer ram is also 10-bits wide. the 10-bit data can be read in one of four different formats. the form<1:0> bits select the format. each of the output fo rmats translates to a 16-bit result on the data bus. write data will always be in right justified (integer) format. figure 20-3: a/d output data formats ram contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 read to bus: signed fractional (1.15) d09 d08d07d06d05d04d03d02d01d00000000 fractional (1.15)d09d08d07d06d05d04d03d02d01d00000000 signed integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 integer 000000d09d08d07d06d05d04d03d02d01d00
? 2005 microchip technology inc. preliminary ds70135c-page 137 DSPIC30F4011/4012 20.12 configuring analog port pins the use of the adpcfg and tris registers control the operation of the a/d port pi ns. the port pins that are desired as analog inputs mu st have their correspond- ing tris bit set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independ ent of the state of the ch0sa<3:0>/ch0sb<3:0> bits and the tris bits. when reading the port register, all pins configured as analog input channels will read as cleared. pins configured as digital in puts will not convert an ana- log input. analog levels on an y pin that is defined as a digital input (including the anx pins), may cause the input buffer to consume cu rrent that exceeds the device specifications. 20.13 connection considerations the analog inputs have diodes to v dd and v ss as esd protection. this requires that the analog input be between v dd and v ss . if the input voltage exceeds this range by greater than 0.3v (e ither direction), one of the diodes becomes forward biased and it may damage the device if the input current specification is exceeded. an external rc filter is sometimes added for anti- aliasing of the input signal. the r component should be selected to ensure that th e sampling time requirements are satisfied. any external components connected (via high impedance) to an anal og input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin.
DSPIC30F4011/4012 ds70135c-page 138 preliminary ? 2005 microchip technology inc. table 20-1: adc register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state adcbuf0 0280 ? ? ? ? ? ? adc data buffer 0 0000 00uu uuuu uuuu adcbuf1 0282 ? ? ? ? ? ? adc data buffer 1 0000 00uu uuuu uuuu adcbuf2 0284 ? ? ? ? ? ? adc data buffer 2 0000 00uu uuuu uuuu adcbuf3 0286 ? ? ? ? ? ? adc data buffer 3 0000 00uu uuuu uuuu adcbuf4 0288 ? ? ? ? ? ? adc data buffer 4 0000 00uu uuuu uuuu adcbuf5 028a ? ? ? ? ? ? adc data buffer 5 0000 00uu uuuu uuuu adcbuf6 028c ? ? ? ? ? ? adc data buffer 6 0000 00uu uuuu uuuu adcbuf7 028e ? ? ? ? ? ? adc data buffer 7 0000 00uu uuuu uuuu adcbuf8 0290 ? ? ? ? ? ? adc data buffer 8 0000 00uu uuuu uuuu adcbuf9 0292 ? ? ? ? ? ? adc data buffer 9 0000 00uu uuuu uuuu adcbufa 0294 ? ? ? ? ? ? adc data buffer 10 0000 00uu uuuu uuuu adcbufb 0296 ? ? ? ? ? ? adc data buffer 11 0000 00uu uuuu uuuu adcbufc 0298 ? ? ? ? ? ? adc data buffer 12 0000 00uu uuuu uuuu adcbufd 029a ? ? ? ? ? ? adc data buffer 13 0000 00uu uuuu uuuu adcbufe 029c ? ? ? ? ? ? adc data buffer 14 0000 00uu uuuu uuuu adcbuff 029e ? ? ? ? ? ? adc data buffer 15 0000 00uu uuuu uuuu adcon1 02a0 adon ?adsidl ? ? ? form<1:0> ssrc<2:0> ? simsam asam samp done 0000 0000 0000 0000 adcon2 02a2 vcfg<2:0> ? ? cscna chps<1:0> bufs ? smpi<3:0> bufm alts 0000 0000 0000 0000 adcon3 02a4 ? ? ? samc<4:0> adrc ? adcs<5:0> 0000 0000 0000 0000 adchs 02a6 ch123nb<1:0> ch123sb ch0nb ch0s b<3:0> ch123na<1:0> ch123sa ch0na ch0sa<3:0> 0000 0000 0000 0000 adpcfg 02a8 ? ? ? ? ? ? ? pcfg8* pcfg7* pcfg6* pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 adcssl 02aa ? ? ? ? ? ? ? cssl8* cssl*7 cssl6* cssl5 cs sl4 cssl3 cssl2 cssl1 cssl0 0000 0000 0000 0000 legend: u = uninitialized bit * not available on dspic30f4012
? 2005 microchip technology inc. preliminary ds70135c-page 139 DSPIC30F4011/4012 21.0 system integration there are several features intended to maximize sys- tem reliability, minimize co st through elimination of external components, provide power saving operating modes and offer code protection: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - programmable brown-out reset (bor) watchdog timer (wdt) power saving modes (sleep and idle) code protection unit id locations in-circuit serial programming (icsp) dspic30f devices have a watchdog timer, which is permanently enabled via the co nfiguration bits, or can be software controlled. it runs off its own rc oscillator for added reliability. there ar e two timers that offer nec- essary delays on power-up. one is the oscillator start- up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power- up timer (pwrt), which provides a delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. severa l oscillator options are also made available to allow the part to fit a wide variety of applications. in the idle mo de, the clock sources are still active, but the cpu is shut-off. the rc oscillator option saves system cost, while the lp crystal option saves power. 21.1 oscillator system overview the dspic30f oscillator system has the following modules and features: various external and inte rnal oscillator options as clock sources an on-chip pll to boos t internal operating frequency a clock switching mech anism between various clock sources programmable clock post scaler for system power savings a fail-safe clock monitor (fscm) that detects clock failure and takes fail-safe measures clock control register osccon configuration bits for ma in oscillator selection table 21-1 provides a su mmary of the dspic30f oscillator operating modes. a simplified diagram of the oscillator system is shown in figure 21-1. configuration bits determine the clock source upon power-on reset (por) and brown-out reset (bor). thereafter, the clock sour ce can be changed between permissible clock source s. the osccon register controls the clock switchi ng and reflects system clock related status bits. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030).
DSPIC30F4011/4012 ds70135c-page 140 preliminary ? 2005 microchip technology inc. table 21-1: oscillator operating modes oscillator mode description xtl 200 khz-4 mhz crystal on osc1:osc2 xt 4 mhz-10 mhz crystal on osc1:osc2 xt w/ pll 4x 4 mhz-10 mhz crys tal on osc1:osc2, 4x pll enabled xt w/ pll 8x 4 mhz-10 mhz crys tal on osc1:osc2, 8x pll enabled xt w/ pll 16x 4 mhz-10 mhz crys tal on osc1:osc2, 16x pll enabled (1) lp 32 khz crystal on sosco:sosci (2) hs 10 mhz-25 mhz crystal ec external clock input (0-40 mhz) ecio external clock input (0-40 mhz), osc2 pin is i/o ec w/ pll 4x external clock input (0-40 mhz), osc2 pin is i/o, 4x pll enabled (1) ec w/ pll 8x external clock input (0-40 mhz), osc2 pin is i/o, 8x pll enabled (1) ec w/ pll 16x external clock input (0-40 mhz), osc2 pin is i/o, 16x pll enabled (1) erc external rc oscillator, osc2 pin is f osc /4 output (3) ercio external rc oscillator, osc2 pin is i/o (3) frc 8 mhz internal rc oscillator frc w/ pll 4x 8 mhz internal rc oscillator, 4x pll enabled frc w/ pll 8x 8 mhz internal rc oscillator, 8x pll enabled frc w/ pll 16x 7.5 mhz internal rc oscillator, 16x pll enabled lprc 512 khz internal rc oscillator note 1: dspic30f maximum operating frequ ency of 120 mhz must be met. 2: lp oscillator can be conveniently shared as system clock, as well as real-time clock for timer1. 3: requires external r and c. fr equency operation up to 4 mhz.
? 2005 microchip technology inc. preliminary ds70135c-page 141 DSPIC30F4011/4012 figure 21-1: oscillator system block diagram primary osc1 osc2 sosco sosci oscillator 32 khz lp clock and control block switching oscillator x4, x8, x16 pll primary oscillator stability detector stability detector secondary oscillator programmable clock divider oscillator start-up timer fail-safe clock monitor (fscm) internal fast rc oscillator (frc) internal low power rc oscillator (lprc) pwrsav instruction wake-up request oscillator configuration bits system clock oscillator trap to timer1 lprc frc secondary osc por done primary osc f pll post<1:0> 2 fcksm<1:0> 2 pll lock cosc<1:0> nosc<1:0> oswen cf
DSPIC30F4011/4012 ds70135c-page 142 preliminary ? 2005 microchip technology inc. 21.2 oscillator configurations 21.2.1 initial clock source selection while coming out of power- on reset or brown-out reset, the device selects its clock source based on: a) fos<1:0> configuration bits that select one of four oscillator groups. b) and fpr<3:0> configur ation bits that select one of 13 oscillator cho ices within the primary group. the selection is as shown in table 21-2. 21.2.2 oscillator start-up timer (ost) in order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an oscillator start-up timer is included. it is a simple 10-bit counter that counts 1024 t osc cycles before releasing the oscillator clock to the rest of the system. the time-out period is designated as t ost . the t ost time is involved every time the oscillator has to restart (i.e., on por, bor and wake-up from sleep). the oscillator start-up timer is applied to the lp oscillator, xt, xtl and hs modes (upon wake-up from sleep, por and bor) for the primary oscillator. table 21-2: configuration bit values for clock selection 21.2.3 lp oscillator control enabling the lp oscillator is controlled with two elements: 1. the current oscillator group bits cosc<1:0>. 2. the lposcen bit (oscon register). the lp oscillator is on (even during sleep mode) if lposcen = 1 . the lp oscillator is the device clock if: cosc<1:0> = 00 (lp selected as main oscillator) and lposcen = 1 keeping the lp oscillator on at all times allows for a fast switch to the 32 khz system clock for lower power operation. returning to the fa ster main oscillator will still require a start-up time. oscillator mode oscillator source fos1 fos0 fpr3 fpr2 fpr1 fpr0 osc2 function ec primary 1 11011 clko ecio primary 1 11100 i/o ec w/pll 4x primary 1 11101 i/o ec w/pll 8x primary 1 11110 i/o ec w/pll 16x primary 1 11111 i/o erc primary 1 11001 clko ercio primary 1 11000 i/o xt primary 1 10100 osc2 xt w/pll 4x primary 1 10101 osc2 xt w/pll 8x primary 1 10110 osc2 xt w/pll 16x primary 1 10111 osc2 xtl primary 1 10000 osc2 hs primary 1 10010 osc2 frc w/pll 4x primary 1 10001 i/o frc w/pll 8x primary 1 11010 i/o frc w/pll 16x primary 1 10011 i/o lp secondary 0 0 ???? (notes 1, 2) frc internal frc 0 1 ???? (notes 1, 2) lprc internal lprc 1 0 ???? (notes 1, 2) note 1: osc2 pin function is determined by the prim ary oscillator mode selection (fpr<3:0>). 2: note that osc1 pin cannot be used as an i/o pin, even if the secondary oscil lator or an internal clock source is selected at all times.
? 2005 microchip technology inc. preliminary ds70135c-page 143 DSPIC30F4011/4012 21.2.4 phase locked loop (pll) the pll multiplies the clock which is generated by the primary oscillator. the pll is selectable to have either gains of x4, x8, and x16. input and output frequency ranges are summarized in table 21-3. table 21-3: pll frequency range the pll features a lock output, which is asserted when the pll enters a phase lo cked state. should the loop fall out of lock (e.g., due to noise), the lock signal will be rescinded. the state of this signal is reflected in the read only lock bit in the osccon register. 21.2.5 fast rc oscillator (frc) the frc oscillator is a fast (8 mhz nominal) internal rc oscillator. this oscillat or is intended to provide reasonable device operati ng speeds without the use of an external crystal, cera mic resonator or rc network. using the x4, x8 and x16 pll options, higher operational frequencies can be generated. the dspic30f operates from the frc oscillator when- ever the current oscillator se lection control bits in the osccon register (osccon<13:12>) are set to ? 01 ?. there are four tuning bits (tun<3:0>) for the frc oscillator in the osccon register. these tuning bits allow the frc oscillator fr equency to be adjusted as close to 8 mhz as possible, depending on the device operating conditions. the f rc oscillator frequency has been calibrated during fa ctory testing. table 21-4 describes the adjustment range of the tun<3:0> bits. table 21-4: frc tuning 21.2.6 low power rc oscillator (lprc) the lprc oscillator is a co mponent of the watchdog timer (wdt) and oscillates at a nominal frequency of 512 khz. the lprc oscillator is the clock source for the power-up timer (pwrt) circuit, wdt and clock monitor circuits. it may also be used to provide a low frequency clock source option for applications where power consumption is critical, and timing accuracy is not required. the lprc oscillator is alwa ys enabled at a power-on reset, because it is the clo ck source for the pwrt. after the pwrt expires, th e lprc oscillator will remain on if one of the following is true: the fail-safe clock monitor is enabled the wdt is enabled the lprc oscillator is selected as the system clock via the cosc<1:0> control bits in the osccon register if one of the above conditions is not true, the lprc will shut-off after the pwrt expires. fin pll multiplier fout 4 mhz-10 mhz x4 16 mhz-40 mhz 4 mhz-10 mhz x8 32 mhz-80 mhz 4 mhz-7.5 mhz x16 64 mhz-120 mhz tun<3:0> bits frc frequency 0111 + 10.5% 0110 + 9.0% 0101 + 7.5% 0100 + 6.0% 0011 + 4.5% 0010 + 3.0% 0001 + 1.5% 0000 center frequency (oscillator is running at calibrated frequency) 1111 - 1.5% 1110 - 3.0% 1101 - 4.5% 1100 - 6.0% 1011 - 7.5% 1010 - 9.0% 1001 - 10.5% 1000 - 12.0% note 1: osc2 pin function is determined by the primary oscillator mode selection (fpr<3:0>). 2: note that osc1 pin cannot be used as an i/o pin, even if the secondary oscillator or an internal clock source is selected at all times.
DSPIC30F4011/4012 ds70135c-page 144 preliminary ? 2005 microchip technology inc. 21.2.7 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue to operate even in the event of an oscillator failure. the fscm function is enabled by appropriately programming the fcksm configuration bits (clock switch and monitor selection bits) in the f osc device configuration register. if t he fscm function is enabled, the lprc internal oscillator wi ll run at all times (except during sleep mode) and will not be subject to control by the swdten bit. in the event of an oscillator failure, the fs cm will gen- erate a clock failure trap event and will switch the sys- tem clock over to the frc os cillator. the user will then have the option to either at tempt to restart the oscillator or execute a controlled sh utdown. the user may decide to treat the trap as a warm reset by simply loading the reset address into the oscillato r fail trap vector. in this event, the cf (clock fail) status bit (osccon<3>) is also set whenever a clock failure is recognized. in the event of a clock failure, the wdt is unaffected and continues to run on the lprc clock. if the oscillator has a very slow start-up time coming out of por, bor or sleep, it is possible that the pwrt timer will expire before the oscillator has started. in such cases, t he fscm will be activated and the fscm will initiate a cl ock failure trap, and the cosc<1:0> bits are loaded with frc oscillator selec- tion. this will effectively shut -off the original oscillator that was trying to start. the user may detect this situation and restart the oscillator in the clock fail trap isr. upon a clock failure detect ion, the fscm module will initiate a clock switch to the frc oscillator as follows: 1. the cosc bits (osccon<13:12>) are loaded with the frc oscillator selection value. 2. cf bit is set (osccon<3>). 3. oswen control bit (osccon<0>) is cleared. for the purpose of clock sw itching, the clock sources are sectioned into four groups: 1. primary 2. secondary 3. internal frc 4. internal lprc the user can switch between these functional groups, but cannot switch between options within a group. if the primary group is selected, then the choice within the group is always determined by the fpr<3:0> configuration bits. the osccon register holds the control and status bits related to clock switching. cosc<1:0>: read only status bits always reflect the current oscillator group in effect. nosc<1:0>: control bits which are written to indicate the new oscilla tor group of choice. - on por and bor, cosc<1:0> and nosc<1:0> are both loaded with the configuration bit values fos<1:0>. lock: the lock status bit indicates a pll lock. cf: read only status bit indicating if a clock fail detect has occurred. oswen: control bit changes from a ? 0 ? to a ? 1 ? when a clock transition sequence is initiated. clearing the oswen control bit will abort a clock transition in progress (used for hang-up situations). if configuration bits fcksm<1:0> = 1x , then the clock switching and fail-safe clock monitor functions are disabled. this is the defau lt configuration bit setting. if clock switching is disa bled, then the fos<1:0> and fpr<3:0> bits directly cont rol the oscillator selection and the cosc<1:0> bits do not control the clock selection. however, these bits will reflect the clock source selection. 21.2.8 protection against accidental writes to osccon a write to the osccon register is intentionally made difficult because it contro ls clock switching and clock scaling. to write to the osccon lo w byte, the following code sequence must be execut ed without any other instructions in between: byte write ? 0x46 ? to osccon low byte write ? 0x57 ? to osccon low byte write is allowed for one instruction cycle . write the desired value or use bit manipulation instruction. to write to the osccon high byte, the following instructions must be executed without any other instructions in between: byte write ? 0x78 ? to osccon high byte write ? 0x9a ? to osccon high byte write is allowed for one instruction cycle . write the desired value or use bit manipulation instruction. note: the application should not attempt to switch to a clock of frequency lower than 100 khz when the fail-safe clock monitor is enabled. if such clock switching is performed, the device may generate an oscillator fail trap and switch to the fast rc oscillator.
? 2005 microchip technology inc. preliminary ds70135c-page 145 DSPIC30F4011/4012 21.3 reset the DSPIC30F4011/4012 differentiates between vari- ous kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during normal operation) e) programmable brown-out reset (bor) f) reset instruction g) reset cause by trap lockup (trapr) h) reset caused by illegal opcode, or by using an uninitialized w register as an address pointer (iopuwr) different registers are affected in different ways by var- ious reset conditions. most registers are not affected by a wdt wake-up, since this is viewed as the resump- tion of normal operation. status bits from the rcon register are set or cleared di fferently in different reset situations, as indicated in table 21-5. these bits are used in software to determin e the nature of the reset. a block diagram of the on-c hip reset circuit is shown in figure 21-2. a mclr noise filter is provided in the mclr reset path. the filter detects and ignores small pulses. internally generated resets do not drive mclr pin low. figure 21-2: reset system block diagram 21.3.1 por: power-on reset a power-on event will gener ate an internal por pulse when a v dd rise is detected. the reset pulse will occur at the por circuit threshold voltage (v por ), which is nominally 1.85v. the device supply voltage character- istics must meet specified st arting voltage and rise rate requirements. the por pulse will reset a por timer and place the device in t he reset state. the por also selects the device clock source identified by the oscil- lator configuration fuses. the por circuit inserts a small delay, t por , which is nominally 10 s and ensures that the device bias cir- cuits are stable. furthermore, a user selected power- up time-out (t pwrt ) is applied. the t pwrt parameter is based on device configuration bits and can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. the total delay is at device power-up t por + t pwrt . when these delays have expired, sysrst will be negated on the next leading edge of the q1 clock , and the pc will jump to the reset vector. the timing for the sysrst signal is shown in figure 21-3 through figure 21-5. s r q mclr v dd v dd rise detect por sysrst sleep or idle brown-out reset boren reset instruction wdt module digital glitch filter bor trap conflict illegal opcode/ uninitialized w register
DSPIC30F4011/4012 ds70135c-page 146 preliminary ? 2005 microchip technology inc. figure 21-3: time-out sequence on power-up (mclr tied to v dd ) figure 21-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 21-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd internal por pwrt time-out ost time-out internal reset mclr t pwrt t ost v dd internal por pwrt time-out ost time-out internal reset mclr v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
? 2005 microchip technology inc. preliminary ds70135c-page 147 DSPIC30F4011/4012 21.3.1.1 por with long crystal start-up time (with fscm enabled) the oscillator start-up circuitr y is not linked to the por circuitry. some crystal circuits (especially low fre- quency crystals) will have a relatively long start-up time. therefore, one or more of the following conditions is possible after the por timer and the pwrt have expired: the oscillator circuit has not begun to oscillate. the oscillator start-up ti mer has not expired (if a crystal oscillator is used). the pll has not achieved a lock (if pll is used). if the fscm is enabled and one of the above conditions is true, then a clock failur e trap will occur. the device will automatically switch to the frc oscillator and the user can switch to the desired crystal oscillator in the trap isr. 21.3.1.2 operating without fscm and pwrt if the fscm is disabled and the power-up timer (pwrt) is also disabled, t hen the device will exit rap- idly from reset on power- up. if the clock source is frc, lprc, extrc or ec, it will be active immediately. if the fscm is disabled a nd the system clock has not started, the device will be in a frozen state at the reset vector until the system clock starts. from the user?s perspective, the device will appear to be in reset until a system clock is available. 21.3.2 bor: programmable brown-out reset the bor (brown-out reset) module is based on an internal voltage reference circuit. the main purpose of the bor module is to generat e a device reset when a brown-out condition occurs. brown-out conditions are generally caused by glitch es on the ac mains (i.e., missing portions of the ac cycle waveform due to bad power transmission lines or voltage sags due to exces- sive current draw when a large inductive load is turned on). the bor module allows selection of one of the follow- ing voltage trip points: 2.0v 2.7v 4.2v 4.5v a bor will generate a reset pulse which will reset the device. the bor will select the clock source, based on the device configuration bit values (fos<1:0> and fpr<3:0>). furthermore, if an oscillator mode is selected, the bor will activa te the oscillator start-up timer (ost). the system clock is held until ost expires. if the pll is used, then the clock will be held until the lock bit (osccon<5>) is ? 1 ?. concurrently, the por time-out (t por ) and the pwrt time-out (t pwrt ) will be applied before the internal reset is released. if t pwrt = 0 and a crystal oscillator is being used, then a nominal delay of t fscm = 100 s is applied. the total delay in this case is (t por + t fscm ). the bor status bit (rcon<1>) will be set to indicate that a bor has occurred. the bor circuit, if enabled, will continue to operate while in sleep or idle modes and will reset the device should v dd fall below the bor threshold voltage. figure 21-6: external power-on reset circuit (for slow v dd power-up) note: the bor voltage trip points indicated here are nominal values provided for design guidance only. note: dedicated supervisory devices, such as the mcp1xx and mcp8xx, may also be used as an external power-on reset circuit. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r should be suitably chosen so as to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 should be suitably chosen so as to limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown due to elec- trostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd dspic30f mclr
DSPIC30F4011/4012 ds70135c-page 148 preliminary ? 2005 microchip technology inc. table 21-5 shows the reset conditions for the rcon register. since the control bits within the rcon regis- ter are r/w, the information in the table implies that all the bits are negated prior to the action specified in the condition column. table 21-5: initialization condition for rcon register case 1 table 21-6 shows a second example of the bit conditions for the rcon register. in this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column. table 21-6: initialization condition for rcon register case 2 condition program counter trapr iopuwr extr swr wdto idle sleep por bor power-on reset 0x000000 000000011 brown-out reset 0x000000 000000001 mclr reset during normal operation 0x000000 001000000 software reset during normal operation 0x000000 000100000 mclr reset during sleep 0x000000 001000100 mclr reset during idle 0x000000 001001000 wdt time-out reset 0x000000 000010000 wdt wake-up pc + 2 000010100 interrupt wake-up from sleep pc + 2 (1) 000000100 clock failure trap 0x000004 000000000 trap reset 0x000000 100000000 illegal operation trap 0x000000 010000000 legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' note 1: when the wake-up is due to an enabl ed interrupt, the pc is loaded with the corresponding interrupt vector. condition program counter trapr iopuwr extr swr wdto idle sleep por bor power-on reset 0x000000 000000011 brown-out reset 0x000000 uuuuuuu01 mclr reset during normal operation 0x000000 uu10000uu software reset during normal operation 0x000000 uu01000uu mclr reset during sleep 0x000000 uu1u001uu mclr reset during idle 0x000000 uu1u010uu wdt time-out reset 0x000000 uu00100uu wdt wake-up pc + 2 uuuu1u1uu interrupt wake-up from sleep pc + 2 (1) uuuuuu1uu clock failure trap 0x000004 uuuuuuuuu trap reset 0x000000 1uuuuuuuu illegal operation reset 0x000000 u1uuuuuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' note 1: when the wake-up is due to an enable d interrupt, the pc is loaded with the corresponding interrupt vector.
? 2005 microchip technology inc. preliminary ds70135c-page 149 DSPIC30F4011/4012 21.4 watchdog timer (wdt) 21.4.1 watchdog timer operation the primary function of th e watchdog timer (wdt) is to reset the processor in the event of a software mal- function. the wdt is a free running timer, which runs off an on-chip rc oscillator , requiring no external com- ponent. therefore, the wdt timer will continue to oper- ate even if the main processor clock (e.g., the crystal oscillator) fails. 21.4.2 enabling and disabling the wdt the watchdog timer can be ?enabled? or ?disabled? only through a configuratio n bit (fwdten) in the configuration register fwdt. setting fwdten = 1 enables the watchdog timer. the enabling is done when programming the device. by default, after chip-erase, fwdten bit = 1 . any device programmer capable of programming dspic30f devices allows programming of this and other configuration bits. if enabled, the wdt will increment until it overflows or ?times out?. a wdt time-out will force a device reset (except during sleep). to pr event a wdt time-out, the user must clear the watchdog timer using a clrwdt instruction. if a wdt times out during sl eep, the device will wake- up. the wdto bit in the rco n register will be cleared to indicate a wake-up resulting from a wdt time-out. setting fwdten = 0 allows user so ftware to enable/ disable the watchdog timer via the swdten (rcon<5>) control bit. 21.5 power saving modes there are two power saving st ates that can be entered through the execution of a special instruction, pwrsav . these are: sleep and idle. the format of the pwrsav instruction is as follows: pwrsav , where ? parameter ? defines idle or sleep mode. 21.5.1 sleep mode in sleep mode, the clock to the cpu and peripherals is shutdown. if an on-chip oscilla tor is being used, it is shutdown. the fail-safe clock monito r is not functional during sleep, since there is no cl ock to monitor. however, lprc clock remains active if wdt is operational during sleep. the brown-out protection circuit and the low voltage detect circuit, if enabled, wi ll remain functional during sleep. the processor wakes up from sleep if at least one of the following conditions has occurred: any interrupt that is individually enabled and meets the required priority level any reset (por, bor and mclr ) wdt time-out on waking up from sleep mode, the processor will restart the same clock that was active prior to entry into sleep mode. when clo ck switching is enabled, bits cosc<1:0> will deter mine the oscillator source that will be used on wake-up. if clock switch is disabled, then there is only one system clock. if the clock source is an oscillator, the clock to the device will be held off unti l ost times out (indicating a stable oscillator). if pll is used, the system clock is held off until lock = 1 (indicating that the pll is sta- ble). in either case, t por , t lock and t pwrt delays are applied. if ec, frc, lprc or extrc oscillators are used, then a delay of t por (~ 10 s) is applied. this is the smallest delay possible on wa ke-up from sleep. moreover, if lp oscillator was active during sleep, and lp is the oscillator used on wake-up, then the start-up delay will be equal to t por . pwrt delay and ost timer delay are not applied. in order to have the small- est possible start-up delay when waking up from sleep, one of these faster wake- up options should be selected before entering sleep. note: if a por or bor occurred, the selection of the oscillator is based on the fos<1:0> and fpr<3:0> configuration bits.
DSPIC30F4011/4012 ds70135c-page 150 preliminary ? 2005 microchip technology inc. any interrupt that is indi vidually enable d (using the corresponding ie bit) and meets the prevailing priority level will be able to wake-u p the processor. the proces- sor will process the interr upt and branch to the isr. the sleep status bit in rcon register is set upon wake-up. all resets will wake-up the processor from sleep mode. any reset, other than por, will set the sleep status bit. in a por, th e sleep bit is cleared. if watchdog timer is enabled, then the processor will wake-up from sleep mode upon wdt time-out. the sleep and wdto status bits are both set. 21.5.2 idle mode in idle mode, the clock to the cpu is shutdown while peripherals keep running. un like sleep mode, the clock source remains active. several peripherals have a co ntrol bit in each module, that allows them to operate during idle. lprc fail-safe clock remains active if clock failure detect is enabled. the processor wakes up from id le if at least one of the following conditions is true: on any interrupt that is individually enabled (ie bit is ? 1 ?) and meets the requ ired priority level on any reset (por, bor, mclr ) on wdt time-out upon wake-up from idle mode, the clock is re-applied to the cpu and instruction execution begins immedi- ately, starting with the instruction following the pwrsav instruction. any interrupt that is indivi dually enabled (using ie bit) and meets the prevailing prio rity level will be able to wake-up the processor. the processor will process the interrupt and branch to the isr. the idle status bit in rcon register is set upon wake-up. any reset, other than por, wi ll set the idle status bit. on a por, the id le bit is cleared. if watchdog timer is enabled, then the processor will wake-up from idle mode up on wdt time-out. the idle and wdto status bits are both set. unlike wake-up from sleep, there are no time delays involved in wake-up from idle. 21.6 device configuration registers the configuration bits in each device configuration register specify some of the device modes and are pro- grammed by a device prog rammer, or by using the in-circuit serial prog ramming? (icsp?) feature of the device. each device configuration register is a 24- bit register, but only the lowe r 16 bits of each register are used to hold configuration data. there are four device configuration registers available to the user: 1. f os c (0xf80000): oscillator configuration register 2. fwdt (0xf80002): watchdog timer configuration register 3. fborpor (0xf80004): bor and por configuration register 4. fgs (0xf8000a): general code segment configuration register the placement of the config uration bits is automatically handled when you select the device in your device pro- grammer. the desired state of the configuration bits may be specified in the so urce code (dependent on the language tool used), or th rough the programming inter- face. after the device has been programmed, the appli- cation software may read the configuration bit values through the table read instru ctions. for additional infor- mation, please refer to th e programming specifications of the device. note: in spite of various delays applied (t por , t lock and t pwrt ), the crystal oscillator (and pll) may not be active at the end of the time-out (e.g., for low frequency crys- tals. in such cases), if fscm is enabled, then the device will detect this as a clock failure and process the clock failure trap, the frc oscillator will be enabled, and the user will have to re-enable the crystal oscillator. if fscm is not enabled, then the device will simply suspend execution of code until the clock is stable, and will remain in sleep until the oscillator clock has started. note: if the code protection configuration fuse bits (fgs and fgs) have been programmed, an erase of the entire code-protected device is only possible at voltages v dd 4.5v.
? 2005 microchip technology inc. preliminary ds70135c-page 151 DSPIC30F4011/4012 21.7 in-circuit debugger when mplab icd2 is select ed as a debugger, the in-circuit debugging functionality is enabled. this function allows simple debugging functions when used with mplab ide. when th e device has this feature enabled, some of the reso urces are not available for general use. these resource s include the first 80 bytes of data ram and two i/o pins. one of four pairs of debug i/o pins may be selected by the user using configurat ion options in mplab ide. these pin pairs are named emud/emuc, emud1/ emuc1, emud2/emuc2 and mud3/emuc3. in each case, the selected emud pin is the emulation/ debug data line, and the emuc pin is the emulation/ debug clock line. these pins will interface to the mplab icd 2 module available from microchip. the selected pair of debug i/o pins is used by mplab icd 2 to send commands and receive responses, as well as to send and receive data. to use the in-circuit debugger function of th e device, the design must implement icsp connections to mclr , v dd , v ss , pgc, pgd and the selected emudx/emucx pin pair. this gives rise to two possibilities: 1. if emud/emuc is selected as the debug i/o pin pair, then only a 5-pin interface is required, as the emud and emuc pin functions are multi- plexed with the pgd and pgc pin functions in all dspic30f devices. 2. if emud1/emuc1, emud2/emuc2 or emud3/ emuc3 is selected as the debug i/o pin pair, then a 7-pin interface is required, as the emudx/emucx pin functions (x = 1, 2 or 3) are not multiplexed with the pgd and pgc pin functions.
DSPIC30F4011/4012 ds70135c-page 152 preliminary ? 2005 microchip technology inc. table 21-7: system integration register map table 21-8: device configuration register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr . bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state rcon 0740 trapr iopuwr bgst ? extr swr swdten wdto sleep idle bor por depends on type of reset. osccon 0742 tun3 tun2 cosc<1:0> tun1 tun0 nosc<1:0> post<1:0> lock ?cf ? lposcen oswen depends on configuration bits. legend: u = uninitialized bit file name addr. bits 23-16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 fosc f80000 ? fcksm<1:0> ? ? ? ? fos<1:0> ? ? ? ? fpr<3:0> fwdt f80002 ? fwdten ? ? ? ? ? ? ? ? ? fwpsa<1:0> fwpsb<3:0> fborpor f80004 ?mclren ? ? ? ? pwmpin hpol lpol boren ? borv<1:0> ? ? fpwrt<1:0> fgs f8000a ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? gcp gwrp
? 2005 microchip technology inc. preliminary ds70135c-page 153 DSPIC30F4011/4012 22.0 instruction set summary the dspic30f instruction set adds many enhancements to the previous picmicro ? instruction sets, while maintaining an easy migration from picmicro instruction sets. most instructions are a single program memory word (24-bits). only three instructions require two program memory locations. each single-word instruct ion is a 24-bit word divided into an 8-bit opcode which specifies the instruction type, and one or more oper ands which further specify the operation of the instruction. the instruction set is high ly orthogonal and is grouped into five basic categories: word or byte-oriented operations bit-oriented operations literal operations dsp operations control operations table 22-1 shows the general symbols used in describing the instructions. the dspic30f instruction set summary in table 22-2 lists all the instructions al ong with the status flags affected by each instruction. most word or byte-orient ed w register instructions (including barrel shift instructions) have three operands: the first source operand, which is typically a register ?wb? without any address modifier the second source operand, which is typically a register ?ws? with or wi thout an address modifier the destination of the resu lt, which is typically a register ?wd? with or wi thout an address modifier however, word or byte-oriente d file register instructions have two operands: the file register specified by the value ?f? the destination, which could either be the file register ?f? or the w0 register, which is denoted as ?wreg? most bit oriented instructions (including simple rotate/ shift instructions) have two operands: the w register (with or without an address modi- fier) or file register (specified by the value of ?ws? or ?f?) the bit in the w register or file register (specified by a literal value, or indirectly by the contents of register ?wb?) the literal instructions that involve data movement may use some of the following operands: a literal value to be loaded into a w register or file register (specified by the value of ?k?) the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: the first source operand, which is a register ?wb? without any address modifier the second source operand, which is a literal value the destination of the resu lt (only if not the same as the first source opera nd), which is typically a register ?wd? with or wi thout an address modifier the mac class of dsp instructions may use some of the following operands: the accumulator (a or b) to be used (required operand) the w registers to be used as the two operands the x and y address space pre-fetch operations the x and y address space pre-fetch destinations the accumulator write back destination the other dsp instructions do not involve any multiplication, and may include: the accumulator to be used (required) the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier the amount of shift, specified by a w register ?wn? or a literal value the control instructions may use some of the following operands: a program memory address the mode of the table read and table write instructions all instructions are a singl e word, except for certain double-word instructions, which were made double- word instructions so that a ll the required information is available in these 48-bits. in the second word, the 8 msb?s are 0?s. if this second word is executed as an instruction (by itself), it will execute as a nop . note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030).
DSPIC30F4011/4012 ds70135c-page 154 preliminary ? 2005 microchip technology inc. most single word instructio ns are executed in a single instruction cycle, unless a condi tional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the ex ecution takes two instruction cycles with the addi tional instruction cycle(s) executed as a nop . notable exceptions are the bra (uncondi- tional/computed branch), indirect call/goto , all table reads and writes and return/retfie instruc- tions, which are single word instructions, but take two or three cycles. certain instructions that involve skip- ping over the subsequent instruction, require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single word or two-word instruction. moreover, double-word moves require two cycles. the double-word instructions execute in two instruction cycles. note: for more details on the instruction set, refer to the dspic30f programmer?s reference manual (ds70030). table 22-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation register bit field .b byte mode selection .d double-word mode selection .s shadow register select .w word mode selection (default) acc one of two accumulators {a, b} awb accumulator write back destination address register {w13, [w13]+=2} bit4 4-bit bit selection field (used in word addressed instructions) {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, zero expr absolute address, label or ex pression (resolved by the linker) f file register address {0x0000...0x1fff} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; lsb must be 0 none field does not require an entry, may be blank oa, ob, sa, sb dsp status bits: acca overflow, accb overflow, acca saturate, accb saturate pc program counter slit10 10-bit signed literal {-512...511} slit16 16-bit signed literal {-32768...32767} slit6 6-bit signed literal {-16...16}
? 2005 microchip technology inc. preliminary ds70135c-page 155 DSPIC30F4011/4012 wb base w register {w0..w15} wd destination w register { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working register pair (direct addressing) wm*wm multiplicand and multiplier working re gister pair for square instructions {w4*w4,w5*w5,w6*w6,w7*w7} wm*wn multiplicand and multiplier working register pair for dsp instructions {w4*w5,w4*w6,w4*w7,w5*w6,w5*w7,w6*w7} wn one of 16 working registers {w0..w15} wnd one of 16 destination working registers {w0..w15} wns one of 16 source working registers {w0..w15} wreg w0 (working register used in file register instructions) ws source w register { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space pre-fetch address register for dsp instructions {[w8]+=6, [w8]+=4, [w8]+=2, [w8], [w8]-=6, [w8]-=4, [w8]-=2, [w9]+=6, [w9]+=4, [w9]+=2, [w9], [w9]-=6, [w9]-=4, [w9]-=2, [w9+w12],none} wxd x data space pre-fetch destination register for dsp instructions {w4..w7} wy y data space pre-fetch address register for dsp instructions {[w10]+=6, [w10]+=4, [w10]+=2, [w 10], [w10]-=6, [w10]-=4, [w10]-=2, [w11]+=6, [w11]+=4, [w11]+=2 , [w11], [w11]-=6, [w11]-=4, [w11]-=2, [w11+w12], none} wyd y data space pre-fetch destination register for dsp instructions {w4..w7} table 22-1: symbols used in opcode descriptions (continued) field description
DSPIC30F4011/4012 ds70135c-page 156 preliminary ? 2005 microchip technology inc. table 22-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected 1 add add acc add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic ri ght shift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra oa,expr branch if accumula tor a overflow 1 1 (2) none bra ob,expr branch if accumula tor b overflow 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra sa,expr branch if accumula tor a saturated 1 1 (2) none bra sb,expr branch if accumula tor b saturated 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none 8 bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none 9 btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none
? 2005 microchip technology inc. preliminary ds70135c-page 157 DSPIC30F4011/4012 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z 13 btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z 14 call call lit23 call subroutine 2 2 none call wn call indirect subroutine 1 2 none 15 clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none clr acc,wx,wxd,wy,wyd,awb cle ar accumulator 1 1 oa,ob,sa,sb 16 clrwdt clrwdt clear watchdog timer 1 1 wdto,sleep 17 com com f f = f 11n,z com f,wreg wreg = f 11n,z com ws,wd wd = ws 11n,z 18 cp cp f compare f with wreg 1 1 c,dc,n,ov,z cp wb,#lit5 compare wb with lit5 1 1 c,dc,n,ov,z cp wb,ws compare wb with ws (wb - ws) 1 1 c,dc,n,ov,z 19 cp0 cp0 f compare f with 0x0000 1 1 c,dc,n,ov,z cp0 ws compare ws with 0x0000 1 1 c,dc,n,ov,z 20 cp1 cp1 f compare f with 0xffff 1 1 c,dc,n,ov,z cp1 ws compare ws with 0xffff 1 1 c,dc,n,ov,z 21 cpb cpb f compare f with wreg, with borrow 1 1 c,dc,n,ov,z cpb wb,#lit5 compare wb with lit 5, with borrow 1 1 c,dc,n,ov,z cpb wb,ws compare wb with ws, with borrow (wb - ws - c ) 1 1 c,dc,n,ov,z 22 cpseq cpseq wb, wn compare wb with wn, skip if = 1 1 (2 or 3) none 23 cpsgt cpsgt wb, wn compare wb with wn, skip if > 1 1 (2 or 3) none 24 cpslt cpslt wb, wn compare wb with wn, skip if < 1 1 (2 or 3) none 25 cpsne cpsne wb, wn compare wb with wn, skip if 11 (2 or 3) none 26 daw daw wn wn = decimal adjust wn 1 1 c 27 dec dec f f = f -1 1 1 c,dc,n,ov,z dec f,wreg wreg = f -1 1 1 c,dc,n,ov,z dec ws,wd wd = ws - 1 1 1 c,dc,n,ov,z 28 dec2 dec2 f f = f -2 1 1 c,dc,n,ov,z dec2 f,wreg wreg = f -2 1 1 c,dc,n,ov,z dec2 ws,wd wd = ws - 2 1 1 c,dc,n,ov,z table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected
DSPIC30F4011/4012 ds70135c-page 158 preliminary ? 2005 microchip technology inc. 29 disi disi #lit14 disable interrupts for k instruction cycles 1 1 none 30 div div.s wm,wn signed 16/16-bit in teger divide 1 18 n,z,c, ov div.sd wm,wn signed 32/16-bit int eger divide 1 18 n,z,c, ov div.u wm,wn unsigned 16/16-bit in teger divide 1 18 n,z,c, ov div.ud wm,wn unsigned 32/16-bit in teger divide 1 18 n,z,c, ov 31 divf divf wm,w n signed 16/16-bit fractional divide 1 18 n,z,c, ov 32 do do #lit14,expr do code to pc+expr, lit14+1 times 2 2 none do wn,expr do code to pc+expr, (wn)+1 times 2 2 none 33 ed ed wm*wm,acc,wx,wy,wxd euclidean dist ance ( no accumulate) 1 1 oa,ob,oab, sa,sb,sab 34 edac edac wm*wm,acc,wx,wy,wx d euclidean distance 1 1 oa,ob,oab, sa,sb,sab 35 exch exch wns,wnd swap wns with wnd 1 1 none 36 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 37 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 38 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 39 goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none 40 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 41 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 42 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 43 lac lac wso,#slit4,acc load accumulator 1 1 oa,ob,oab, sa,sb,sab 44 lnk lnk #lit14 link frame pointer 1 1 none 45 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical righ t shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 46 mac mac wm*wn,acc,wx,wxd,wy,wyd, awb multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd square and accumulate 1 1 oa,ob,oab, sa,sb,sab 47 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 n,z mov f,wreg move f to wreg 1 1 n,z mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 n,z mov.d wns,wd move double from w(ns):w(ns +1 ) to wd 1 2 none mov.d ws,wnd mov e double from ws to w(nd +1 ):w(nd) 1 2 none 48 movsac movsac acc,wx,w xd,wy,wyd,awb pre-fetch and store accumulator 1 1 none 49 mpy mpy wm*wn, acc,wx,wxd,wy,wyd multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm ,acc,wx,wxd,wy,wyd square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 50 mpy.n mpy.n wm*wn,acc,wx,wxd,wy,w yd -(multiply wm by wn) to accumulator 1 1 none table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected
? 2005 microchip technology inc. preliminary ds70135c-page 159 DSPIC30F4011/4012 51 msc msc wm*wm,acc,wx,wxd,wy,wyd, awb multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 52 mul mul.ss wb,ws,wnd {wnd+1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd+1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(ws) 11none mul.su wb,#lit5,wnd {wnd+1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(lit5) 11none mul f w3:w2 = f * wreg 1 1 none 53 neg neg acc negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 54 nop nop no operation 1 1 none nopr no operation 1 1 none 55 pop pop f pop f from to p-of-stack (tos) 1 1 none pop wdo pop from top-of-s tack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd+1) 12none pop.s pop shadow registers 1 1 all 56 push push f push f to t op-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns+1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none 57 pwrsav pwrsav #lit 1 go into sleep or idle mode 1 1 wdto,sleep 58 rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none 59 repeat repeat #lit14 repeat next in struction lit14+1 times 1 1 none repeat wn repeat next instruction (wn)+1 times 1 1 none 60 reset reset software device reset 1 1 none 61 retfie retfie return from interrupt 1 3 (2) none 62 retlw retlw #lit10,wn return with literal in wn 1 3 (2) none 63 return return return from subroutine 1 3 (2) none 64 rlc rlc f f = rotate lef t through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 65 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 66 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z 67 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 68 sac sac acc,#slit4,wdo store accumulator 1 1 none sac.r acc,#slit4,wdo store rounded accumulator 1 1 none 69 se se ws,wnd wnd = sign extended ws 1 1 c,n,z 70 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected
DSPIC30F4011/4012 ds70135c-page 160 preliminary ? 2005 microchip technology inc. 71 sftac sftac acc,wn arithmetic shift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 arithmetic shift ac cumulator by s lit6 1 1 oa,ob,oab, sa,sb,sab 72 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 73 sub sub acc subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f - wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f - wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn - lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb - ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb - lit5 1 1 c,dc,n,ov,z 74 subb subb f f = f - wreg - (c ) 1 1 c,dc,n,ov,z subb f,wreg wreg = f - wreg - (c ) 1 1 c,dc,n,ov,z subb #lit10,wn wn = wn - lit10 - (c ) 1 1 c,dc,n,ov,z subb wb,ws,wd wd = wb - ws - (c ) 1 1 c,dc,n,ov,z subb wb,#lit5,wd wd = wb - lit5 - (c ) 1 1 c,dc,n,ov,z 75 subr subr f f = wreg - f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg - f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws - wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 - wb 1 1 c,dc,n,ov,z 76 subbr subbr f f = wreg - f - (c ) 1 1 c,dc,n,ov,z subbr f,wreg wreg = wreg -f - (c ) 1 1 c,dc,n,ov,z subbr wb,ws,wd wd = ws - wb - (c ) 1 1 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 - wb - (c ) 1 1 c,dc,n,ov,z 77 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 78 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none 79 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none 80 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 81 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 82 ulnk ulnk unlink frame pointer 1 1 none 83 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 84 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected
? 2005 microchip technology inc. preliminary ds70135c-page 161 DSPIC30F4011/4012 23.0 development support the picmicro ? microcontrollers are supported with a full range of hardware an d software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers -mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer - mplab pm3 device programmer low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? - picdem msc - microid ? -can - powersmart ? -analog 23.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to too ls with increasing flexibility and power. 23.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files th at contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
DSPIC30F4011/4012 ds70135c-page 162 preliminary ? 2005 microchip technology inc. 23.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debug ging, the compilers provide symbol information that is optimized to the mplab ide debugger. 23.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from pr ecompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library file s of precompiled code. when a routine from a library is call ed from a source file, only the modules that contain that routine will be linked in with the application. this al lows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code mainta inability by grouping related modules together flexible creation of libra ries with easy module listing, replacement, de letion and extraction 23.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties and afford fine control of the compiler code generator. mplab c30 is distributed wi th a complete ansi c standard library. all library functions have been vali- dated and conform to the an si c library standard. the library includes functions for string manipulation, dynamic memory allocation , data conversion, time- keeping and math functions (trigonometric, exponential and hyperbolic). the comp iler provides symbolic information for high-level source debugging with the mplab ide. 23.6 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from sym bolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire d spic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 23.7 mplab sim software simulator the mplab sim software simu lator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and st imuli can be applied from a file, or user defined key pr ess, to any pin. the execu- tion can be performed in single-step, execute until break or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers t he flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 23.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcon trollers on an instruction level. on any given instruction, the data areas can be examined or modified and st imuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for au tomated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optim ize time intensive dsp routines.
? 2005 microchip technology inc. preliminary ds70135c-page 163 DSPIC30F4011/4012 23.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the pr oduct development engineer with a complete microcont roller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, build ing, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, tr igger and data monitoring features. interchangeable pr ocessor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circu it emulator system has been designed as a real-t ime emulation system with advanced features that ar e typically found on more expensive development tool s. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 23.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the pr oduct development engineer with a complete microcontrol ler design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulat or is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory and the ability to view variables in real-time. the mplab ice 4000 in-circu it emulator system has been designed as a real-t ime emulation system with advanced features that ar e typically found on more expensive development tool s. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 23.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run- time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debu g source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral re gisters. running at full speed enables testing har dware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 23.12 pro mate ii universal device programmer the pro mate ii is a univers al, ce compliant device programmer with programmabl e voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instruct ions and error messages and a modular detachable so cket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify and program picmicro devices wi thout a pc connection. it can also set code protection in this mode. 23.13 mplab pm3 device programmer the mplab pm3 is a universal, ce compliant device programmer with programmabl e voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modular de tachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand- alone mode, the mplab pm3 device programmer can read, verify and program picmicro devices without a pc connection. it can also se t code protection in this mode. mplab pm3 connects to the host pc via an rs-232 or usb cable. mplab pm3 has high-speed communications and optimize d algorithms for quick programming of large memo ry devices and incorpo- rates an sd/mmc card for fi le storage and secure data applications.
DSPIC30F4011/4012 ds70135c-page 164 preliminary ? 2005 microchip technology inc. 23.14 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development envi ronment software makes using the programmer simp le and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 23.15 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic1 7c43 and pic17c44. all necessary hardware and so ftware is included to run basic demo programs. th e sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the cir cuitry for additional appli- cation components. featur es include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 23.16 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip de vice that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit featur es a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 23.17 picdem 2 plus demonstration board the picdem 2 plus demons tration board supports many 18, 28 and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional app lication components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds and sample pic18f452 and pic16f877 flash microcontrollers. 23.18 picdem 3 pic16c92x demonstration board the picdem 3 demonstrat ion board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 23.19 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 family of microcontrollers . picdem 4 is intended to showcase the many features of these low pin count parts, including lin and motor control using eccp. special provisions are ma de for low-power operation with the supercapacitor circ uit and jumpers allow on- board hardware to be disabled to eliminate current draw in this mode. included on the demo board are pro- visions for crystal, rc or canned oscillator modes, a five volt regulator for use wi th a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for programming via icsp and development with mplab icd 2, 2 x 16 liquid crystal display, pcb footprints for h-bridge motor driver, li n transceiver and eeprom. also included are: header fo r expansion, eight leds, four potentiometers, three push buttons and a proto- typing area. included with th e kit is a pic16f627a and a pic18f1320. tutorial firm ware is included along with the user?s guide.
? 2005 microchip technology inc. preliminary ds70135c-page 165 DSPIC30F4011/4012 23.20 picdem 17 demonstration board the picdem 17 demonstratio n board is an evaluation board that demonstrates t he capabilities of several microchip microcontrolle rs, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is include d. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to repr ogram the device for user tailored application development. the picdem 17 demonstration board suppor ts program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion. 23.21 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstrat ion board serves to assist development of the pic18c601/ 801 family of microchip microcontrollers. it provid es hardware implementation of both 8-bit multiplexed/ demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 23.22 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 23.23 pickit? 1 flash starter kit a complete ?development sy stem in a box?, the pickit flash starter kit includes a convenient multi-section board for programming, eval uation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates un der a simple windows gui. the pickit 1 starter kit includes the user?s guide (on cd rom), pickit 1 tutorial software and code for various applications. also included are mplab ? ide (integrated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 23.24 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this boar d provides the basis for future usb products. 23.25 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kit s and demonstration software for these products. k ee l oq evaluation and prog ramming tools for microchip?s hcs secure data products can developers kit fo r automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc and flow rate sensor check the microchip web pa ge and the latest product selector guide for the comple te list of demonstration and evaluation kits.
DSPIC30F4011/4012 ds70135c-page 166 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 167 DSPIC30F4011/4012 24.0 electrical characteristics this section provides an overview of ds pic30f electrical characteristics. additio nal information will be provided in future revisions of this document as it becomes available. for detailed information about the dspic3 0f architecture and core, refer to dspic30f family reference manual (ds70046). absolute maximum ratings for the dspic 30f family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional opera tion of the device at these or any other conditions above the parameters indicated in t he operation listings of this specification is not implied. absolute maximum ratings (?) ambient temperature under bias...... .............................................. ............................................. ............-40c to +125c storage temperature .............................. ........................................ ...................................... .................. -65c to +150c voltage on any pin with respect to v ss (except v dd and mclr ) (note 1) ..................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ........................................ ........................................ ......................... -0.3v to +5.5v voltage on mclr with respect to v ss ................................................ ................................... .................... 0v to +13.25v maximum current out of v ss pin ................................... ............................................. ........................................... 300 ma maximum current into v dd pin (note 2) ......................................... ............................................. ..........................250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ........................................ .............................................. ....................20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ....................................... ........................................ .................... 20 ma maximum output current sunk by any i/o pin..................... ................................... ............................. .....................25 ma maximum output current sourced by any i/o pin ................................ ............................. ..................... ..................25 ma maximum current sunk by all ports .. .................................. ................................... ....................... .........................200 ma maximum current sourced by all ports (note 2) ........................................ ........................................ ....................200 ma note 1: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latchup. thus, a series re sistor of 50-100 ? should be used when applyi ng a ?low? level to the mclr /v pp pin, rather than pulling this pin directly to v ss . 2: maximum allowable current is a func tion of device maximum power diss ipation. see table 24-2. 24.1 dc characteristics ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating onl y and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. ex posure to maximum rating conditions for extended periods may affe ct device reliability. table 24-1: operating mips vs. voltage v dd range temp range max mips dspic30f401x-30i dspic30f 401x-20i dspic30f401x-20e 4.5-5.5v -40c to 85c 30 20 ? 4.5-5.5v -40c to 125c ? ? 20 3.0-3.6v -40c to 85c 20 15 ? 3.0-3.6v -40c to 125c ? ? 15 2.5-3.0v -40c to 85c 10 7.5 ?
DSPIC30F4011/4012 ds70135c-page 168 preliminary ? 2005 microchip technology inc. table 24-2: thermal operating conditions rating symbol min typ max unit dspic30f401x-30i operating junction temperature range t j -40 +125 c operating ambient temperature range t a -40 +85 c dspic30f401x-20i operating junction temperature range t j -40 +150 c operating ambient temperature range t a -40 +85 c dspic30f401x-20e operating junction temperature range t j -40 +150 c operating ambient temperature range t a -40 +125 c power dissipation: internal chip power dissipation: p d p int + p i / o w i/o pin power dissipation: maximum allowed power dissipation p dmax (t j - t a ) / ja w table 24-3: thermal packaging characteristics characteristic symbol typ max unit notes package thermal resistance, 28-pin spdip (sp) ja 41 c/w 1 package thermal resistance, 28-pin soic (so) ja 45 c/w 1 package thermal resistance, 40-pin dip (p) ja 37 c/w 1 package thermal resistance, 44-pin tqfp (10x10x1mm) ja 40 c/w 1 package thermal resistance, 44-pin qfn ja 28 c/w 1 note 1: junction to ambient therma l resistance, theta-ja ( ja ) numbers are achieved by package simulations. table 24-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions operating voltage (2) dc10 v dd supply voltage 2.5 ? 5.5 v industrial temperature dc11 v dd supply voltage 3.0 ? 5.5 v extended temperature dc12 v dr ram data retention voltage (3) ?1.5?v dc16 v por v dd start voltage to ensure internal power-on reset signal ?v ss ?v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms 0-5v in 0.1 sec 0-3v in 60 ms note 1: data in ?typ? column is at 5v, 25 c unless otherwise stated. paramete rs are for design guidance only and are not tested. 2: these parameters are characterize d but not tested in manufacturing. 3: this is the limit to which v dd can be lowered with out losing ram data. p int v dd i dd i oh ? () = p i / o v dd v oh ? {} i oh () v ol i ol () + =
? 2005 microchip technology inc. preliminary ds70135c-page 169 DSPIC30F4011/4012 table 24-5: dc characteristics: operating current (i dd ) dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions operating current (i dd ) (2) dc20 ? ? ma -40c 3.3v 1 mips ec mode dc20a 2.5 ? ma 25c dc20b ? ? ma 85c dc20c ? ? ma 125c dc20d ? ? ma -40c 5v dc20e 4.5 ? ma 25c dc20f ? ? ma 85c dc20g ? ? ma 125c dc23 ? ? ma -40c 3.3v 4 mips ec mode, 4x pll dc23a 11 ? ma 25c dc23b ? ? ma 85c dc23c ? ? ma 125c dc23d ? ? ma -40c 5v dc23e 18 ? ma 25c dc23f ? ? ma 85c dc23g ? ? ma 125c dc24 ? ? ma -40c 3.3v 10 mips ec mode, 4x pll dc24a 25 ? ma 25c dc24b ? ? ma 85c dc24c ? ? ma 125c dc24d ? ? ma -40c 5v dc24e 43 ? ma 25c dc24f ? ? ma 85c dc24g ? ? ma 125c dc25 ? ? ma -40c 3.3v 8 mips ec mode, 8x pll dc25a 24 ? ma 25c dc25b ? ? ma 85c dc25c ? ? ma 125c dc25d ? ? ma -40c 5v dc25e 41 ? ma 25c dc25f ? ? ma 85c dc25g ? ? ma 125c note 1: data in ?typical? column is at 5v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 2: the supply current is mainly a function of the operatin g voltage and frequency. ot her factors such as i/o pin loading and switching rate, oscillator type, inter nal code execution pattern and temperature also have an impact on the current consumpt ion. the test co nditions for all i dd measurements are as follows: osc1 driven with external square wave fr om rail to rail. all i/o pins are configured as inputs and pulled to v dd . mclr = v dd , wdt, fscm, lvd and bor are disabled. cpu, sram, program memory and data memory are operational. no per ipheral modules are operating.
DSPIC30F4011/4012 ds70135c-page 170 preliminary ? 2005 microchip technology inc. dc27 ? ? ma -40c 3.3v 20 mips ec mode, 8x pll dc27a 52 ? ma 25c dc27b ? ? ma 85c dc27c ? ? ma -40c 5v dc27d 94 ? ma 25c dc27e ? ? ma 85c dc27f ? ? ma 125c dc28 ? ? ma -40c 3.3v 16 mips ec mode, 16x pll dc28a 41 ? ma 25c dc28b ? ? ma 85c dc28c ? ? ma -40c 5v dc28d 74 ? ma 25c dc28e ? ? ma 85c dc28f ? ? ma 125c dc29 ? ? ma -40c 5v 30 mips ec mode, 16x pll dc29a 132 ? ma 25c dc29b ? ? ma 85c dc29c ? ? ma 125c dc30 ? ? ma -40c 3.3v frc (~ 2 mips) dc30a 7 ? ma 25c dc30b ? ? ma 85c dc30c ? ? ma 125c dc30d ? ? ma -40c 5v dc30e 12 ? ma 25c dc30f ? ? ma 85c dc30g ? ? ma 125c dc31 ? ? ma -40c 3.3v lprc (~ 512 khz) dc31a 1 ? ma 25c dc31b ? ? ma 85c dc31c ? ? ma 125c dc31d ? ? ma -40c 5v dc31e 2 ? ma 25c dc31f ? ? ma 85c dc31g ? ? ma 125c table 24-5: dc characteristics: operating current (i dd ) (continued) dc characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions operating current (i dd ) (2) note 1: data in ?typical? column is at 5v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 2: the supply current is mainly a function of the operatin g voltage and frequency. other factors such as i/o pin loading and switching rate, oscillat or type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: osc1 driven with external square wave from rail to rail. all i/o pins are co nfigured as inputs and pulled to v dd . mclr = v dd , wdt, fscm, lvd and bor are disabled. cpu, sram, program memory and data memory are operational. no per ipheral modules are operating.
? 2005 microchip technology inc. preliminary ds70135c-page 171 DSPIC30F4011/4012 table 24-6: dc characteristics: idle current (i idle ) dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions idle current (i idle ): core off clock on base current (2) dc40 ? ? ma -40c 3.3v 1 mips ec mode dc40a 1.5 ? ma 25c dc40b ? ? ma 85c dc40c ? ? ma 125c dc40d ? ? ma -40c 5v dc40e 3 ? ma 25c dc40f ? ? ma 85c dc40g ? ? ma 125c dc43 ? ? ma -40c 3.3v 4 mips ec mode, 4x pll dc43a 8 ? ma 25c dc43b ? ? ma 85c dc43c ? ? ma 125c dc43d ? ? ma -40c 5v dc43e 12 ? ma 25c dc43f ? ? ma 85c dc43g ? ? ma 125c dc44 ? ? ma -40c 3.3v 10 mips ec mode, 4x pll dc44a 17 ? ma 25c dc44b ? ? ma 85c dc44c ? ? ma 125c dc44d ? ? ma -40c 5v dc44e 27 ? ma 25c dc44f ? ? ma 85c dc44g ? ? ma 125c dc45 ? ? ma -40c 3.3v 8 mips ec mode, 8x pll dc45a 15 ? ma 25c dc45b ? ? ma 85c dc45c ? ? ma 125c dc45d ? ? ma -40c 5v dc45e 26 ? ma 25c dc45f ? ? ma 85c dc45g ? ? ma 125c note 1: data in ?typical? column is at 5v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 2: base i idle current is measured with core off, clock on an d all modules turned off.
DSPIC30F4011/4012 ds70135c-page 172 preliminary ? 2005 microchip technology inc. dc47 ? ? ma -40c 3.3v 20 mips ec mode, 8x pll dc47a 33 ? ma 25c dc47b ? ? ma 85c dc47c ? ? ma -40c 5v dc47d 56 ? ma 25c dc47e ? ? ma 85c dc47f ? ? ma 125c dc48 ? ? ma -40c 3.3v 16 mips ec mode, 16x pll dc48a 26 ? ma 25c dc48b ? ? ma 85c dc48c ? ? ma -40c 5v dc48d 46 ? ma 25c dc48e ? ? ma 85c dc48f ? ? ma 125c dc49 ? ? ma -40c 5v 30 mips ec mode, 16x pll dc49a 85 ? ma 25c dc49b ? ? ma 85c dc49c ? ? ma 125c dc50 ? ? ma -40c 3.3v frc (~ 2 mips) dc50a 4 ? ma 25c dc50b ? ? ma 85c dc50c ? ? ma 125c dc50d ? ? ma -40c 5v dc50e 7 ? ma 25c dc50f ? ? ma 85c dc50g ? ? ma 125c dc51 ? ? ma -40c 3.3v lprc (~ 512 khz) dc51a 0.5 ? ma 25c dc51b ? ? ma 85c dc51c ? ? ma 125c dc51d ? ? ma -40c 5 v dc51e 0.9 ? ma 25c dc51f ? ? ma 85c dc51g ? ? ma 125c table 24-6: dc characteristics: idle current (i idle ) (continued) dc characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions idle current (i idle ): core off clock on base current (2) note 1: data in ?typical? column is at 5v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 2: base i idle current is measured with core off, clock on and all modules turned off.
? 2005 microchip technology inc. preliminary ds70135c-page 173 DSPIC30F4011/4012 table 24-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions power down current (i pd ) (2) dc60 ? ? a -40c 3.3v base power down current (3) dc60a 1 ? a25c dc60b ? ? a85c dc60c ? ? a 125c dc60d ? ? a -40c 5v dc60e 1 ? a25c dc60f ? ? a85c dc60g ? ? a 125c dc61 ? ? a -40c 3.3v watchdog timer current: ? i wdt (3) dc61a 4 ? a25c dc61b ? ? a85c dc61c ? ? a 125c dc61d ? ? a -40c 5v dc61e 10 ? a25c dc61f ? ? a85c dc61g ? ? a 125c dc62 ? ? a -40c 3.3v timer 1 w/32 khz crystal: ? i ti 32 (3) dc62a 5.5 ? a25c dc62b ? ? a85c dc62c ? ? a 125c dc62d ? ? a -40c 5v dc62e 7.5 ? a25c dc62f ? ? a85c dc62g ? ? a 125c dc63 ? ? a -40c 3.3v bor on: ? i bor (3) dc63a 32 ? a25c dc63b ? ? a85c dc63c ? ? a 125c dc63d ? ? a -40c 5v dc63e 38 ? a25c dc63f ? ? a85c dc63g ? ? a 125c note 1: data in the typical column is at 5v, 25c unless otherwise stated. paramete rs are for design guidance only and are not tested. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as inputs and pulled high. lvd, bor, wdt, etc. are all switched off. 3: the ? current is the additional curren t consumed when the module is e nabled. this current should be added to the base i pd current.
DSPIC30F4011/4012 ds70135c-page 174 preliminary ? 2005 microchip technology inc. table 24-8: dc characteristics: i/o pin input specifications dc characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v il input low voltage (2) di10 i/o pins: with schmitt trigger buffer v ss ?0.2v dd v di15 mclr v ss ?0.2v dd v di16 osc1 (in xt, hs and lp modes) v ss ?0.2v dd v di17 osc1 (in rc mode) (3) v ss ?0.3v dd v di18 sda, scl tbd ? tbd v sm bus disabled di19 sda, scl tbd ? tbd v sm bus enabled v ih input high voltage (2) di20 i/o pins: with schmitt trigger buffer 0.8 v dd ?v dd v di25 mclr 0.8 v dd ?v dd v di26 osc1 (in xt, hs and lp modes) 0.7 v dd ?v dd v di27 osc1 (in rc mode) (3) 0.9 v dd ?v dd v di28 sda, scl tbd ? tbd v sm bus disabled di29 sda, scl tbd ? tbd v sm bus enabled i cnpu cn xx pull-up current (2) di30 50 250 400 av dd = 5v, v pin = v ss di31 tbd tbd tbd av dd = 3v, v pin = v ss i il input leakage current (2)(4)(5) di50 i/o ports ? 0.01 1 av ss v pin v dd , pin at hi-impedance di51 analog input pins ? 0.50 ? av ss v pin v dd , pin at hi-impedance di55 mclr ?0.055 av ss v pin v dd di56 osc1 ? 0.05 5 av ss v pin v dd , xt, hs and lp osc mode note 1: data in ?typ? column is at 5v, 25 c unless otherwise stated. paramete rs are for design guidance only and are not tested. 2: these parameters are characterize d but not tested in manufacturing. 3: in rc oscillator configuration, the osc1/clkl pin is a schmitt trigger input. it is not recommended that the dspic30f device be driven with an external clock while in rc mode. 4: the leakage current on the mclr pin is strongly dependent on the a pplied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 5: negative current is defined as current sourced by the pin.
? 2005 microchip technology inc. preliminary ds70135c-page 175 DSPIC30F4011/4012 figure 24-1: brown-out reset characteristics table 24-9: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v ol output low voltage (2) do10 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 5v ??tbdvi ol = 2.0 ma, v dd = 3v do16 osc2/clkout ? ? 0.6 v i ol = 1.6 ma, v dd = 5v (rc or ec osc mode) ? ? tbd v i ol = 2.0 ma, v dd = 3v v oh output high voltage (2) do20 i/o ports v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 5v tbd ? ? v i oh = -2.0 ma, v dd = 3v do26 osc2/clkout v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 5v (rc or ec osc mode) tbd ? ? v i oh = -2.0 ma, v dd = 3v capacitive loading specs on output pins (2) do50 c osc 2 osc2/sosc2 pin ? ? 15 pf in xtl, xt, hs and lp modes when external clock is used to drive osc1. do56 c io all i/o pins and osc2 ? ? 50 pf rc or ec osc mode do58 c b scl, sda ? ? 400 pf in i 2 c mode note 1: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. bo10 reset (due to bor) v dd (device in brown-out reset) (device not in brown-out reset) power up time-out bo15
DSPIC30F4011/4012 ds70135c-page 176 preliminary ? 2005 microchip technology inc. table 24-10: electrical characteristics: bor table 24-11: dc characteristics: program and eeprom dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions bo10 v bor bor voltage (2) on v dd transition high to low borv = 00 (3) ? ? ? v not in operating range borv = 01 2.7 ? 2.86 v borv = 10 4.2 ? 4.46 v borv = 11 4.5 ? 4.78 v bo15 v bhys ?5?mv note 1: data in ?typ? column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: 00 values not in usable operating range. dc characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions data eeprom memory (2) d120 e d byte endurance 100k 1m ? e/w -40 c t a +85c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write v min = minimum operating voltage d122 t dew erase/write cycle time ? 2 ? ms d123 t retd characteristic retention 40 100 ? yea r provided no other specifications are violated d124 i dew i dd during programming ? 10 30 ma row erase program flash memory (2) d130 e p cell endurance 10k 100k ? e/w -40 c t a +85c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v eb v dd for bulk erase 4.5 ? 5.5 v d133 v pew v dd for erase/write 3.0 ? 5.5 v d134 t pew erase/write cycle time ? 2 ? ms d135 t retd characteristic retention 40 100 ? yea r provided no other specifications are violated d136 t eb icsp block erase time ? 4 ? ms d137 i pew i dd during programming ? 10 30 ma row erase d138 i eb i dd during programming ? 10 30 ma bulk erase note 1: data in ?typ? column is at 5v , 25c unless otherwise stated. 2: these parameters are characterized but not tested in manufacturing.
? 2005 microchip technology inc. preliminary ds70135c-page 177 DSPIC30F4011/4012 24.2 ac characteristics and timing parameters the information contained in this section defines dspic30f ac charac teristics and timi ng parameters. table 24-12: temperature and voltage specifications ? ac figure 24-2: load conditions for device timing specifications figure 24-3: external clock timing ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended operating voltage v dd range as described in dc spec section 24.0. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 5 pf for osc2 output load condition 1 - for all pins except osc2 load condition 2 - for osc2 osc1 clkout q4 q1 q2 q3 q4 q1 os20 os25 os30 os30 os40 os41 os31 os31
DSPIC30F4011/4012 ds70135c-page 178 preliminary ? 2005 microchip technology inc. table 24-13: external clock timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions os10 f osc external clkin frequency (2) (external clocks allowed only in ec mode) dc 4 4 4 ? ? ? ? 40 10 10 7.5 mhz mhz mhz mhz ec ec with 4x pll ec with 8x pll ec with 16x pll oscillator frequency (2) dc 0.4 4 4 4 4 10 31 ? ? ? ? ? ? ? ? ? ? 7.3728 512 4 4 10 10 10 7.5 25 33 ? ? mhz mhz mhz mhz mhz mhz mhz khz mhz khz rc xtl xt xt with 4x pll xt with 8x pll xt with 16x pll hs lp frc internal lprc internal os20 t osc t osc = 1/f osc ? ? ? ? see parameter os10 for f osc value os25 t cy instruction cycle time (2)(3) 33 ? dc ns see table 24-15 os30 tosl, to s h external clock (2) in (osc1) high or low time .45 x t osc ??nsec os31 tosr, to s f external clock (2) in (osc1) rise or fall time ? ? 20 ns ec os40 tckr clkout rise time (2)(4) ? 6 10 ns os41 tckf clkout fall time (2)(4) ? 6 10 ns note 1: data in ?typ? column is at 5v, 25 c unless otherwise stated. paramete rs are for design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under st andard operating conditions with the device executing code. exceeding these spe cified limits may result in an unstable oscillator operation and/or higher than expect ed current consumption. all devices ar e tested to operate at ?min.? values with an external clock appl ied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ? dc? (no clock) for all devices. 4: measurements are taken in ec or erc modes. the clkout signal is measured on the osc2 pin. clkout is low for the q1-q2 period (1/2 t cy ) and high for the q3-q4 period (1/2 t cy ).
? 2005 microchip technology inc. preliminary ds70135c-page 179 DSPIC30F4011/4012 table 24-15: internal clock timing examples table 24-14: pll clock timing specifications (v dd = 2.5 to 5.5 v) ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions os50 f plli pll input frequency range (2) 4 ? 10 mhz ec, xt modes with pll os51 f sys on-chip pll output (2) 16 ? 120 mhz ec, xt modes with pll os52 t loc pll start-up time (lock time) ? 20 50 s os53 d clk clkout stability (jitter) tbd 1 tbd % measured over 100 ms period note 1: these parameters are characterize d but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. clock oscillator mode f osc (mhz) (1) t cy ( sec) (2) mips (3) w/o pll mips (3) w pll x4 mips (3) w pll x8 mips (3) w pll x16 ec 0.200 20.0 0.05 ? ? ? 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 ? 25 0.16 6.25 ? ? ? xt 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 ? note 1: assumption: oscillator po stscaler is divide by 1. 2: instruction execution cycle time: t cy = 1 / mips. 3: instruction execution frequency: mips = (f osc * pllx) / 4 [since there are 4 q clocks per instruction cycle].
DSPIC30F4011/4012 ds70135c-page 180 preliminary ? 2005 microchip technology inc. table 24-16: ac characteristics: internal rc accuracy ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions internal frc accuracy @ frc freq = 7.37 mhz (1) frc tbd % +25c v dd = 3.0-3.6v tbd % +25c v dd = 4.5-5.5v tbd % -40c t a +85c v dd = 3.0-3.6v tbd % -40c t a +85c v dd = 4.5-5.5v tbd % -40c t a +125c v dd = 4.5-5.5v frc with x4 pll tbd % +25c v dd = 3.0-3.6v tbd % +25c v dd = 4.5-5.5v tbd % -40c t a +85c v dd = 3.0-3.6v tbd % -40c t a +85c v dd = 4.5-5.5v tbd % -40c t a +125c v dd = 4.5-5.5v frc with x8 pll tbd % +25c v dd = 3.0-3.6v tbd % +25c v dd = 4.5-5.5v tbd % -40c t a +85c v dd = 3.0-3.6v tbd % -40c t a +85c v dd = 4.5-5.5v tbd % -40c t a +125c v dd = 4.5-5.5v frc with x16 pll tbd % +25c v dd = 3.0-3.6v tbd % +25c v dd = 4.5-5.5v tbd % -40c t a +85c v dd = 3.0-3.6v tbd % -40c t a +85c v dd = 4.5-5.5v tbd % -40c t a +125c v dd = 4.5-5.5v note 1: frequency calibrated at 25c and 5v. tun bits can be used to compensate for temperature drift.
? 2005 microchip technology inc. preliminary ds70135c-page 181 DSPIC30F4011/4012 table 24-17: ac characteristics: internal rc jitter ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions internal frc jitter @ frc freq = 7.37 mhz (1) frc tbd % +25c v dd = 3.0-3.6v tbd % +25c v dd = 4.5-5.5v tbd % -40c t a +85c v dd = 3.0-3.6v tbd % -40c t a +85c v dd = 4.5-5.5v tbd % -40c t a +125c v dd = 4.5-5.5v frc with x4 pll tbd % +25c v dd = 3.0-3.6v tbd % +25c v dd = 4.5-5.5v tbd % -40c t a +85c v dd = 3.0-3.6v tbd % -40c t a +85c v dd = 4.5-5.5v tbd % -40c t a +125c v dd = 4.5-5.5v frc with x8 pll tbd % +25c v dd = 3.0-3.6v tbd % +25c v dd = 4.5-5.5v tbd % -40c t a +85c v dd = 3.0-3.6v tbd % -40c t a +85c v dd = 4.5-5.5v tbd % -40c t a +125c v dd = 4.5-5.5v frc with x16 pll tbd % +25c v dd = 3.0-3.6v tbd % +25c v dd = 4.5-5.5v tbd % -40c t a +85c v dd = 3.0-3.6v tbd % -40c t a +85c v dd = 4.5-5.5v tbd % -40c t a +125c v dd = 4.5-5.5v note 1: frequency calibrated at 25c and 5v. tun bits ca n be used to compensate for temperature drift. table 24-18: internal rc accuracy ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. characteristic min typ max units conditions lprc @ freq = 512 khz (1) f20 tbd ? tbd % -40c to +85c v dd =3v f21 tbd ? tbd % -40c to +85c v dd =5v note 1: frequency at 25c and 5v.
DSPIC30F4011/4012 ds70135c-page 182 preliminary ? 2005 microchip technology inc. figure 24-4: clkout and i/o timing characteristics table 24-19: clkout and i/o timing requirements ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1)(2)(3) min typ (4) max units conditions do31 t io r port output rise time ? 10 25 ns ? do32 t io f port output fall time ? 10 25 ns ? di35 t inp intx pin high or low time (output) 20 ? ? ns ? di40 t rbp cnx high or low time (input) 2 t cy ? ? ns ? note 1: these parameters are asynchronous event s not related to any internal clock edges 2: measurements are taken in rc mode an d ec mode where clkout output is 4 x t osc . 3: these parameters are characterized but not tested in manufacturing. 4: data in ?typ? column is at 5v , 25c unless otherwise stated. note: refer to figure 24-2 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32
? 2005 microchip technology inc. preliminary ds70135c-page 183 DSPIC30F4011/4012 figure 24-5: reset, watchdog timer, osci llator start-up timer and power-up timer timing characteristics v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset sy11 sy10 sy20 sy13 i/o pins sy13 note: refer to figure 24-2 for load conditions. fscm delay sy35 sy30 sy12
DSPIC30F4011/4012 ds70135c-page 184 preliminary ? 2005 microchip technology inc. table 24-20: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset timing requirements figure 24-6: band gap start-up time characteristics table 24-21: band gap start-up time requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sy10 tmcl mclr pulse width (low) 2 ? ? s -40c to +85c sy11 t pwrt power-up timer period tbd tbd tbd tbd 0 4 16 64 tbd tbd tbd tbd ms -40c to +85c user programmable sy12 t por power on reset delay 3 10 30 s -40c to +85c sy13 t ioz i/o hi-impedance from mclr low or watchdog timer reset ??100ns sy20 t wdt 1 watchdog timer time-out period (no prescaler) 1.8 2.0 2.2 ms v dd = 5v, -40c to +85c t wdt 2 1.9 2.1 2.3 ms v dd = 3v, -40c to +85c sy25 t bor brown-out reset pulse width (3) 100 ? ? sv dd v bor (d034) sy30 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period sy35 t fscm fail-safe clock monitor delay ? 100 ? s -40c to +85c note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v , 25c unless otherwise stated. 3: refer to figure 24-1 and table 24-10 for bor. ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sy40 t bgap band gap start-up time ? 20 50 s defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. rcon<13>status bit note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v , 25c unless otherwise stated. v bgap enable band gap band gap 0v (see note) stable note: band gap is enabled when fborpor<7> is set. sy40
? 2005 microchip technology inc. preliminary ds70135c-page 185 DSPIC30F4011/4012 figure 24-7: timer 1, 2, 3, 4 and 5 exter nal clock timing characteristics table 24-22: timer1 external clock timing requirements ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ max units conditions ta10 t tx h txck high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter ta15 synchronous, with prescaler 10 ? ? ns asynchronous 10 ? ? ns ta11 t tx l txck low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter ta15 synchronous, with prescaler 10 ? ? ns asynchronous 10 ? ? ns ta15 t tx p txck input period synchronous, no prescaler t cy + 10 ? ? ns synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n ? ? ? n = prescale value (1, 8, 64, 256) asynchronous 20 ? ? ns os60 ft1 sosc1/t1ck oscillator input frequency range (o scillator enabled by setting bit tcs (t1con, bit 1)) dc ? 50 khz ta20 t ckextmrl delay from external txck clock edge to timer increment 2 t osc 6 t osc ? note: refer to figure 24-2 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck
DSPIC30F4011/4012 ds70135c-page 186 preliminary ? 2005 microchip technology inc. table 24-23: timer2 and timer4 external clock timing requirements table 24-24: timer3 and timer5 external clock timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ max units conditions tb10 ttxh txck high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter tb15 synchronous, with prescaler 10 ? ? ns tb11 ttxl txck low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter tb15 synchronous, with prescaler 10 ? ? ns tb15 ttxp txck input period synchronous, no prescaler t cy + 10 ? ? ns n = prescale value (1, 8, 64, 256) synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n tb20 t ckextmrl delay from external txck clock edge to timer increment 2 t osc ?6 t osc ? ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ max units conditions tc10 ttxh txck high time synchronous 0.5 t cy + 20 ? ? ns must also meet parameter tc15 tc11 ttxl txck low time synchronous 0.5 t cy + 20 ? ? ns must also meet parameter tc15 tc15 ttxp txck input period synchronous, no prescaler t cy + 10 ? ? ns n = prescale value (1, 8, 64, 256) synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n tc20 t ckextmrl delay from external txck clock edge to timer increment 2 t osc ?6 t osc ?
? 2005 microchip technology inc. preliminary ds70135c-page 187 DSPIC30F4011/4012 figure 24-8: timerq (qei module) externa l clock timing characteristics table 24-25: qei module external clock timing requirements ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions tq10 ttqh tqck high time synchronous, with prescaler t cy + 20 ? ns must also meet parameter tq15 tq11 ttql tqck low time synchronous, with prescaler t cy + 20 ? ns must also meet parameter tq15 tq15 ttqp tqcp input period synchronous, with prescaler 2 * t cy + 40 ? ns ? tq20 t ckextmrl delay from external txck clock edge to timer increment tosc 5 tosc ns ? note 1: these parameters are characterize d but not tested in manufacturing. tq11 tq15 tq10 tq20 qeb poscnt
DSPIC30F4011/4012 ds70135c-page 188 preliminary ? 2005 microchip technology inc. figure 24-9: input capture (capx) timing characteristics table 24-26: input capture timing requirements figure 24-10: output compare module (o cx) timing characteristics table 24-27: output compare module timing requirements ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min max units conditions ic10 tccl icx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns ic11 tcch icx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns ic15 tccp icx input period (2 t cy + 40)/n ? ns n = prescale value (1, 4, 16) note 1: these parameters are characterized but not tested in manufacturing. ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions oc10 tccf ocx output fall time ? 10 25 ns ? oc11 tccr ocx output rise time ? 10 25 ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. paramete rs are for design guidance only and are not tested. ic x ic10 ic11 ic15 note: refer to figure 24-2 for load conditions. ocx oc11 oc10 (output compare note: refer to figure 24-2 for load conditions. or pwm mode)
? 2005 microchip technology inc. preliminary ds70135c-page 189 DSPIC30F4011/4012 figure 24-11: oc/pwm module timing characteristics table 24-28: simple oc/pwm mode timing requirements ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions oc15 t fd fault input to pwm i/o change ? ? 25 ns v dd = 3v -40c to +85c tbd ns v dd = 5v oc20 t flt fault input pulse width ? ? 50 ns v dd = 3v -40c to +85c tbd ns v dd = 5v note 1: these parameters are characterize d but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. ocfa/ocfb ocx oc20 oc15
DSPIC30F4011/4012 ds70135c-page 190 preliminary ? 2005 microchip technology inc. figure 24-12: motor control pwm module fault timing characteristics figure 24-13: motor control pwm module timing characteristics table 24-29: motor control pwm module timing requirements ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions mp10 t fpwm pwm output fall time ? 10 25 ns v dd = 5v -40c to +85c mp11 t rpwm pwm output rise time ? 10 25 ns v dd = 5v -40c to +85c mp12 t fpwm pwm output fall time ? tbd tbd ns v dd = 3v -40c to +85c mp13 t rpwm pwm output rise time ? tbd tbd ns v dd = 3v -40c to +85c mp20 t fd fault input to pwm i/o change ? ? 25 ns v dd = 3v -40c to +85c tbd ns v dd = 5v mp30 t fh minimum pulse width ? ? 50 ns v dd = 3v -40c to +85c tbd ns v dd = 5v note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. flta/b pwmx mp30 mp20 pwmx mp11 mp10 note: refer to figure 24-2 for load conditions.
? 2005 microchip technology inc. preliminary ds70135c-page 191 DSPIC30F4011/4012 figure 24-14: qea/qeb input characteristics table 24-30: quadrature decoder timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) typ (2) max units conditions tq30 t qu l quadrature input low time 6 t cy ?ns ? tq31 t qu h quadrature input high time 6 t cy ?ns ? tq35 t qu in quadrature input period 12 t cy ?ns ? tq36 t qu p quadrature phase period 3 t cy ?ns ? tq40 t quf l filter time to recognize low, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 2) tq41 t quf h filter time to recognize high, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 2) note 1: these parameters are characterize d but not tested in manufacturing. 2: n = index channel digital filter cl ock divide select bits. refer to section 16. ?quadrature encoder interface (qei)? in the dspic30f family reference manual . tq30 tq35 tq31 qea (input) tq30 tq35 tq31 qeb (input) tq36 qeb internal tq40 tq41
DSPIC30F4011/4012 ds70135c-page 192 preliminary ? 2005 microchip technology inc. figure 24-15: qei module index pulse timing characteristics table 24-31: qei index pulse timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min max units conditions tq50 tqil filter time to recognize low, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 2) tq51 tqih filter time to recognize high, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 2) tq55 tqidxr index pulse recognized to position counter reset (ungated index) 3 t cy ?ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: alignment of index pulses to qea and qeb is shown for position coun ter reset timing only. shown for forward direction only (qea leads qe b). same timing applies for revers e direction (qea lags qeb) but index pulse recognition occurs on falling edge. qea (input) ungated index qeb (input) tq55 index internal position tq50 tq51
? 2005 microchip technology inc. preliminary ds70135c-page 193 DSPIC30F4011/4012 figure 24-16: spi module master mode (cke = 0 ) timing characteristics table 24-32: spi master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscl sck x output low time (3) t cy / 2 ? ? ns ? sp11 tsch sck x output high time (3) t cy / 2 ? ? ns ? sp20 tscf sck x output fall time (4 ?1025ns ? sp21 tscr sck x output rise time (4) ?1025ns ? sp30 tdof sdo x data output fall time (4) ?1025ns ? sp31 tdor sdo x data output rise time (4) ?1025ns ? sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge ? ? 30 ns ? sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ? ? ns ? note 1: these parameters are characterize d but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. therefore, the clock g enerated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit14 - - - - - -1 msb in lsb in bit14 - - - -1 sp30 sp31 note: refer to figure 24-2 for load conditions.
DSPIC30F4011/4012 ds70135c-page 194 preliminary ? 2005 microchip technology inc. figure 24-17: spi module master mode (cke = 1 ) timing characteristics table 24-33: spi module master mode (cke = 1 ) timing requirements ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscl sck x output low time (3) t cy / 2 ? ? ns ? sp11 tsch sck x output high time (3) t cy / 2 ? ? ns ? sp20 tscf sck x output fall time (4) ?1025ns ? sp21 tscr sck x output rise time (4) ?1025ns ? sp30 tdof sdo x data output fall time (4) ?1025ns ? sp31 tdor sdo x data output rise time (4) ?1025ns ? sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge ? ? 30 ns ? sp36 tdov2sc, tdov2scl sdo x data output setup to first sck x edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. therefore, the clock ge nerated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins. sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb msb in bit14 - - - - - -1 lsb in bit14 - - - -1 lsb note: refer to figure 24-2 for load conditions. sp11 sp10 sp20 sp21 sp21 sp20 sp40 sp41
? 2005 microchip technology inc. preliminary ds70135c-page 195 DSPIC30F4011/4012 figure 24-18: spi module slave mode (cke = 0 ) timing characteristics table 24-34: spi module slave mode (cke = 0 ) timing requirements ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscl sck x input low time 30 ? ? ns ? sp71 tsch sck x input high time 30 ? ? ns ? sp72 tscf sck x input fall time (3) ?1025ns ? sp73 tscr sck x input rise time (3) ?1025ns ? sp30 tdof sdo x data output fall time (3) ?1025ns ? sp31 tdor sdo x data output rise time (3) ?1025ns ? sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge ? ? 30 ns ? sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ? ? ns ? sp50 tssl2sch, tssl2scl ss x to sck x or sck x input 120 ? ? ns ? sp51 tssh2doz ss x to sdo x output hi-impedance (3) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ss x after sck edge 1.5 t cy +40 ? ? ns ? note 1: these parameters are characterize d but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. 3: assumes 50 pf load on all spi pins. ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi sp50 sp40 sp41 sp30,sp31 sp51 sp35 sdi x msb lsb bit14 - - - - - -1 msb in bit14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 24-2 for load conditions.
DSPIC30F4011/4012 ds70135c-page 196 preliminary ? 2005 microchip technology inc. figure 24-19: spi module slave mode (cke = 1 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi sp50 sp60 sdi x sp30,sp31 msb bit14 - - - - - -1 lsb sp51 msb in bit14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp71 sp70 sp40 sp41 note: refer to figure 24-2 for load conditions.
? 2005 microchip technology inc. preliminary ds70135c-page 197 DSPIC30F4011/4012 table 24-35: spi module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 ts c l sck x input low time 30 ? ? ns ? sp71 tsch sck x input high time 30 ? ? ns ? sp72 tscf sck x input fall time (3) ?1025ns ? sp73 tscr sck x input rise time (3) ?1025ns ? sp30 tdof sdo x data output fall time (3) ?1025ns ? sp31 tdor sdo x data output rise time (3) ?1025ns ? sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge ? ? 30 ns ? sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ? ? ns ? sp50 tssl2sch, ts s l 2 s c l ss x to sck x or sck x input 120 ? ? ns ? sp51 tssh2doz ss to sdo x output hi-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh ts c l 2 s s h ss x after sck x edge 1.5 t cy + 40 ? ? ns ? sp60 tssl2dov sdo x data output valid after ss x edge ? ? 50 ns ? note 1: these parameters are characterize d but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. therefore, the clock g enerated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins.
DSPIC30F4011/4012 ds70135c-page 198 preliminary ? 2005 microchip technology inc. figure 24-20: i 2 c bus start/stop bits timing ch aracteristics (master mode) figure 24-21: i 2 c bus data timing characteristics (master mode) im31 im34 scl sda start condition stop condition im30 im33 note: refer to figure 24-2 for load conditions. im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 scl sda in sda out note: refer to figure 24-2 for load conditions.
? 2005 microchip technology inc. preliminary ds70135c-page 199 DSPIC30F4011/4012 table 24-36: i 2 c bus data timing requirements (master mode) ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min (1) max units conditions im10 t lo : scl clock low time 100 khz mode t cy / 2 (brg + 1) ? s? 400 khz mode t cy / 2 (brg + 1) ? s? 1 mhz mode (2) t cy / 2 (brg + 1) ? s? im11 t hi : scl clock high time 100 khz mode t cy / 2 (brg + 1) ? s? 400 khz mode t cy / 2 (brg + 1) ? s? 1 mhz mode (2) t cy / 2 (brg + 1) ? s? im20 t f : scl sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ?100ns im21 t r : scl sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ?300ns im25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (2) tbd ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? ns ? 400 khz mode 0 0.9 s 1 mhz mode (2) tbd ? ns im30 t su : sta start condition setup time 100 khz mode t cy / 2 (brg + 1) ? s only relevant for repeated start condition 400 khz mode t cy / 2 (brg + 1) ? s 1 mhz mode (2) t cy / 2 (brg + 1) ? s im31 t hd : sta start condition hold time 100 khz mode t cy / 2 (brg + 1) ? s after this period the first clock pulse is generated 400 khz mode t cy / 2 (brg + 1) ? s 1 mhz mode (2) t cy / 2 (brg + 1) ? s im33 t su : sto stop condition setup time 100 khz mode t cy / 2 (brg + 1) ? s? 400 khz mode t cy / 2 (brg + 1) ? s 1 mhz mode (2) t cy / 2 (brg + 1) ? s im34 t hd : sto stop condition 100 khz mode t cy / 2 (brg + 1) ? ns ? hold time 400 khz mode t cy / 2 (brg + 1) ? ns 1 mhz mode (2) t cy / 2 (brg + 1) ? ns im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns ? 400 khz mode ? 1000 ns ? 1 mhz mode (2) ??ns ? im45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (2) tbd ? s im50 c b bus capacitive loading ? 400 pf note 1: brg is the value of the i 2 c baud rate generator. refer to section 21 ?inter-integrated circuit? (i 2 c)? in the dspic30f family reference manual. 2: maximum pin capacitance = 10 pf for all i 2 c pins (for 1 mhz mode only).
DSPIC30F4011/4012 ds70135c-page 200 preliminary ? 2005 microchip technology inc. figure 24-22: i 2 c bus start/stop bits timing characteristics (slave mode) figure 24-23: i 2 c bus data timing characteristics (slave mode) is31 is34 scl sda start condition stop condition is30 is33 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 scl sda in sda out
? 2005 microchip technology inc. preliminary ds70135c-page 201 DSPIC30F4011/4012 table 24-37: i 2 c bus data timing requirements (slave mode) ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min max units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz. 1 mhz mode (1) 0.5 ? s? is11 t hi : scl clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 ? s? is20 t f : scl sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?100ns is21 t r : scl sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?300ns is25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (1) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 ? ns ? 400 khz mode 0 0.9 s 1 mhz mode (1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is31 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is33 t su : sto stop condition setup time 100 khz mode 4.7 ? s? 400 khz mode 0.6 ? s 1 mhz mode (1) 0.6 ? s is34 t hd : sto stop condition 100 khz mode 4000 ? ns ? hold time 400 khz mode 600 ? ns 1 mhz mode (1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns ? 400 khz mode 0 1000 ns 1 mhz mode (1) 0350ns is45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (1) 0.5 ? s is50 c b bus capacitive loading ? 400pf ? note 1: maximum pin capacitance = 10 pf for all i 2 c pins (for 1 mhz mode only).
DSPIC30F4011/4012 ds70135c-page 202 preliminary ? 2005 microchip technology inc. figure 24-24: can module i/o timing characteristics table 24-38: can module i/o timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions ca10 tiof port output fall time ? 10 25 ns ? ca11 tior port output rise time ? 10 25 ns ? ca20 tcwf pulse width to trigger can wakeup filter 500 ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. c x t x pin (output) ca10 ca11 old value new value ca20 c x r x pin (input)
? 2005 microchip technology inc. preliminary ds70135c-page 203 DSPIC30F4011/4012 table 24-39: 10-bit high-speed a/d module specifications ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply greater of v dd - 0.3 or 2.7 lesser of v dd + 0.3 or 5.5 v? ad02 av ss module v ss supply vss - 0.3 v ss + 0.3 v ? reference inputs ad05 v refh reference voltage high avss+2.7 av dd v? ad06 v refl reference voltage low avss av dd - 2.7 v ? ad07 v ref absolute reference voltage avss - 0.3 av dd + 0.3 v ? ad08 i ref current drain ? 200 .001 300 3 a a a/d operating a/d off analog input ad10 v inh -v inl full-scale input span v refl v refh v? ad11 v in absolute input voltage av ss - 0.3 av dd + 0.3 v ? ad12 ? leakage current ? 0.001 0.244 av inl = av ss = v refl = 0v, av dd = v refh = 5v source impedance = 5 k ? ad13 ? leakage current ? 0.001 0.244 av inl = av ss = v refl = 0v, av dd = v refh = 3v source impedance = 5 k ? ad15 r ss switch resistance ? 5k ? ? ? ad16 c sample sample capacitor ? 2.5 pf ? ad17 r in recommended impedance of analog voltage source ?5k ? ? dc accuracy ad20 nr resolution 10 data bits bits ? ad21 inl integral nonlinearity ? 0.5 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad21a inl integral nonlinearity ? 0.5 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad22 dnl differential nonlinearity ? 0.5 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad22a dnl differential nonlinearity ? 0.5 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad23 g err gain error ? 0.75 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad23a g err gain error ? 0.75 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v note 1: because the sample caps will eventually lose char ge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 2: the a/d conversion result never decr eases with an increase in the in put voltage, and has no missing codes.
DSPIC30F4011/4012 ds70135c-page 204 preliminary ? 2005 microchip technology inc. ad24 e off offset error ? 0.75 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad24a e off offset error ? 0.75 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad25 ? monotonicity (2) ? ? ? ? guaranteed ad26 cmrr common-mode rejection ? tbd ? db ? ad27 psrr power supply rejection ratio ?tbd ? db ? ad28 ctlk channel to channel crosstalk ?tbd ? db ? dynamic performance ad30 thd total harmonic distortion ? tbd ? db ? ad31 sinad signal to noise and distortion ?tbd ? db ? ad32 sfdr spurious free dynamic range ?tbd ? db ? ad33 f nyq input signal bandwidth ? ? 250 khz ? ad34 enob effective number of bits ? tbd tbd bits ? table 24-39: 10-bit high-speed a/d mo dule specifications (continued) ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min. typ max. units conditions note 1: because the sample caps will eventually lose c harge, clock rates below 10 kh z can affect linearity performance, especially at elevated temperatures. 2: the a/d conversion result never decreases with an increase in the input vo ltage, and has no missing codes.
? 2005 microchip technology inc. preliminary ds70135c-page 205 DSPIC30F4011/4012 figure 24-25: 10-bit high-speed a/d conversion timing characteristics (chps = 01 , simsam = 0 , asam = 0 , ssrc = 000 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ch0_dischrg ch1_samp ad60 done adif adres( 0 ) adres( 1 ) 1 2 3 4 5 6 9 5 6 8 1 - software sets adcon. samp to start sampling. 2 - sampling starts after discharge period. 3 - software clears adcon. samp to start conversion. 4 - sampling ends, conversion sequence starts. 5 - convert bit 9 . 9 - one t ad for end of conversion. ad50 ch0_samp ch1_dischrg eoc 8 ad55 9 6 - convert bit 8 . 8 - convert bit 0 . execution t samp is described in the dspic30f mcu family reference manual , section 17.
DSPIC30F4011/4012 ds70135c-page 206 preliminary ? 2005 microchip technology inc. figure 24-26: 10-bit high-speed a/d conversion timing characteristics (chps = 01 , simsam = 0 , asam = 1 , ssrc = 111 , samc = 00001 ) ad55 t samp set adon adclk instruction samp ch0_dischrg ch1_samp done adif adres( 0 ) adres( 1 ) 1 2 3 4 5 6 4 5 6 8 1 - software sets adcon. ad on to start ad operation. 2 - sampling starts after discharge period. 3 - convert bit 9 . 4 - convert bit 8 . 5 - convert bit 0 . ad50 ch0_samp ch1_dischrg eoc 7 3 ad55 6 - one t ad for end of conversion. 7 - begin conversion of next channel 8 - sample for time specified by samc. t samp t conv 3 4 execution t samp is described in the dspic30f family reference manual , section 17. t samp is described in the dspic30f family reference manual , section 17.
? 2005 microchip technology inc. preliminary ds70135c-page 207 DSPIC30F4011/4012 table 24-40: 10-bit high-speed a/d conversion timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min. typ max. units conditions clock parameters ad50 t ad a/d clock period 154 256 ns v dd = 5v (note 1) v dd = 2.7v (note 1) ad51 t rc a/d internal rc oscillator period 700 900 1100 ns ? conversion rate ad55 t conv conversion time 13 t ad ns ? ad56 f cnv throughput rate 500 100 ksps ksps v dd = v ref = 5v v dd = v ref = 2.7v ad57 t samp sample time ? 1 t ad ?nsv dd = 3-5.5v timing parameters ad60 t pcs conversion start from sample trigger ??t ad ns ? ad61 t pss sample start from setting sample (samp) bit 0.5 t ad ?1.5 t ad ns ? ad62 t css conversion completion to sample start (asam = 1 ) ??tbdns ? ad63 t dpu time to stabilize analog stage from a/d off to a/d on ??tbd s? note 1: because the sample caps will eventually lose char ge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures.
DSPIC30F4011/4012 ds70135c-page 208 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 209 DSPIC30F4011/4012 25.0 packaging information 25.1 package marking information 28-lead pdip (skinny dip) xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example dspic30f4012 0510017 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example dspic30f4012 0510017 * standard picmicro device marking consists of m icrochip part number, year code, week code and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn dspic example 0510017 30f4012 example DSPIC30F4011 0510017 40-lead pdip xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn 30i/sp 30i/ml legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-f ree jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e 3 e 3 e 30i/so 30i/p
DSPIC30F4011/4012 ds70135c-page 210 preliminary ? 2005 microchip technology inc. package marking information (continued) 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn dspic example 0510017 dspic 0510017 30f4011 30i/ml 30i/pt 30f4011 3 e 3 e
? 2005 microchip technology inc. preliminary ds70135c-page 211 DSPIC30F4011/4012 25.2 package details 28-lead skinny plastic dual in-line (sp) ? 300 mil body (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not inc lude mold flash or protrusions. mold fl ash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic
DSPIC30F4011/4012 ds70135c-page 212 preliminary ? 2005 microchip technology inc. 28-lead plastic small outline (so) ? wide, 300 mil body (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrus ions. mold flash or prot rusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic
? 2005 microchip technology inc. preliminary ds70135c-page 213 DSPIC30F4011/4012 40-lead plastic dual in-line (p) ? 600 mil body (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c eb e p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions sh all not exceed .010? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic
DSPIC30F4011/4012 ds70135c-page 214 preliminary ? 2005 microchip technology inc. 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include m old flash or protrusions. mold flas h or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 e e1 #leads=n1 p b d1 d n 1 2 c l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 ch x 45 significant characteristic
? 2005 microchip technology inc. preliminary ds70135c-page 215 DSPIC30F4011/4012 44-lead plastic quad flat no le ad package (ml) 8x8 mm body (qfn)
DSPIC30F4011/4012 ds70135c-page 216 preliminary ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. preliminary ds70135c-page 217 DSPIC30F4011/4012 index numerics 10-bit high speed a/d a/d acquisition requirements ...... ................ ............ 135 aborting a conversion ............. .................. ............... 134 adchs .............. .................... .................... ............... 131 adcon1 ................... .................. .................. ............ 131 adcon2 ................... .................. .................. ............ 131 adcon3 ................... .................. .................. ............ 131 adcssl.................... .................. .................. ............ 131 adpcfg ................... .................. .................. ............ 131 configuring analog port pins... .................. ............... 137 connection considerations......... .................. ............ 137 conversion operation .............. .................. ............... 133 effects of a reset...... .................. .................. ............ 136 operation during cpu idle mode ................. ............ 136 operation during cpu sleep mode ................ .......... 136 output formats ........... .................. ................ ............ 136 power-down modes ........ ....................... ................... 136 programming the start of conv ersion trigger .......... 134 register map............. .................. .................. ............ 138 result buffer .......... .................. .................. ............... 133 sampling requirements.............. .................. ............ 135 selecting the conversion clock ... ................. ............ 134 selecting the conversion seque nce............. ............ 133 10-bit high speed analog-to-digital (a/d) converter module ....... .................. ................ ............ 131 16-bit up/down position counter mo de................ .............. 86 count direction status ............. ..................... .............. 86 error checking ....................... .................... ................. 86 8-output pwm register map............. .................. .................. ............ 100 a ac characteristics ....... .................... .................. ............... 177 load conditions .......... .................. ................ ............ 177 ac temperature and voltage specif ications .................... 177 address generator units ............... .................... ................. 35 alternate 16-bit timer/c ounter.............. .................. ............ 87 alternate vector table ...... .................. .................. .............. 45 assembler mpasm assembler.................. .................. ............... 161 automatic clock stretch.... .................. .................. ............ 108 during 10-bit addressing (stren = 1)......... ............ 108 during 7-bit addressing (stren = 1)........... ............ 108 receive mode ............. .................. ................ ............ 108 transmit mode ....................... .................... ............... 108 b bandgap start-up time requirements.............. .................. ................ ............ 184 timing characteristics ............. .................. ............... 184 barrel shifter ................ .................... ..................... .............. 22 bit-reversed addressing ............... .................... ................. 38 example .................... .................. .................. .............. 38 implementation ........... .................. .................. ............ 38 modifier values (table) .................. .................. ............ 39 sequence table (16-entry)........... .................. ............ 39 block diagrams 10-bit high speed a/d functional. ................ ............ 132 16-bit timer1 module ............... ..................... .............. 64 16-bit timer4............. .................. .................. .............. 74 16-bit timer5............. .................. .................. .............. 75 32-bit timer4/5 .......... .................. .................. ............. 73 can buffers and protocol engi ne ............... ............. 122 dedicated port structure ........... .................. ............... 57 dsp engine ............... .................. .................. ............. 19 DSPIC30F4011....... .................... .................. ................. 8 dspic30f4012....... .................... .................. ................. 9 external power-on reset circui t ................. ............. 147 i 2 c .................. .................... ..................... ................. 106 input capture mode................. .................... ............... 77 oscillator system................... .................... ............... 141 output compare mode .............. .................. ............... 81 pwm module ................ .................. ............... ............. 92 quadrature encoder interface ..... .................. ............. 85 reset system ............ .................. ................ ............. 145 shared port structure... .................. ............... ............. 58 spi.................. .................... ..................... ................. 102 spi master/slave connection...... ................ ............. 102 uart receiver.......... .................. ................ ............. 114 uart transmitter...... .................. ................ ............. 113 bor characteristics ...... .................. .................. ............... 176 bor. see brown-out reset brown-out reset characteristics......... .................. .................. ............. 175 timing requirements ................ .................. ............. 184 brown-out reset (bor)... .................. .................. ............. 139 c c compilers mplab c17............... .................. ................ ............. 162 mplab c18............... .................. ................ ............. 162 mplab c30............... .................. ................ ............. 162 can module ........... .................... ..................... ................. 121 can1 register map... .................. ................ ............. 128 i/o timing characteristics ....... .................. ............... 202 i/o timing requirements........... .................. ............. 202 overview.................. .................. .................. ............. 121 center aligned pwm ....... .................. .................. ............... 95 clkout and i/o timing characteristics......... .................. .................. ............. 182 requirements ............ .................. ................ ............. 182 code examples data eeprom block erase ....... ................. ............... 54 data eeprom block write ....... .................. ............... 56 data eeprom read.... .................. ............... ............. 53 data eeprom word erase ....... ................. ............... 54 data eeprom word write ....... .................. ............... 55 erasing a row of program memo ry .............. ............. 49 initiating a programming sequence . ................ .......... 50 loading write latches...... ....................... ................... 50 code protection ............. .................. .................. ............... 139 complementary pwm operation....... .................. ............... 95 configuring analog port pins......... .................... ................. 58 control registers ......... .................... .................... ............... 48 nvmadr ................... .................. .................. ............. 48 nvmadru ................... .................. ............... ............. 48 nvmcon...................... .................. ............... ............. 48 nvmkey ................... .................. .................. ............. 48 core overview ............. .................... .................... ............... 15 core register map....... .................... .................... ............... 31 customer change notification serv ice.............. ............... 223 customer notification service ....... .................... ............... 223 customer support.......... .................. .................. ............... 223
DSPIC30F4011/4012 ds70135c-page 218 preliminary ? 2005 microchip technology inc. d data access from program memory using program space visibility ............ .................. ............... 26 data accumulators and adder/subtr actor............ ............... 20 data space write saturation ..... .................. ............... 22 overflow and saturation ............ .................. ............... 20 round logic ................. .................. ................ ............. 21 write back................ .................. .................. ............... 21 data address space ........ .................. .................. ............... 27 alignment ................. .................. .................. ............... 30 alignment (figure) ....... .................. ................ ............. 30 effect of invalid memory acce sses .............. ............... 30 mcu and dsp (mac class) instructions example..... 29 memory map .............. .................. ................ ......... 27, 28 near data space ....... .................. .................. ............. 31 software stack ...................... .................... .................. 31 spaces .............. .................... .................... .................. 30 width................. .................... .................... .................. 30 data eeprom memory .................. ..................... ............... 53 erasing .............. .................... .................... .................. 54 erasing, block .......... .................. .................. ............... 54 erasing, word .......... .................. .................. ............... 54 protection against spurious writ e ................. ............. 56 reading............. .................... .................... .................. 53 write verify .............. .................. .................. ............... 56 writing ............... .................... .................... .................. 55 writing, block ........... .................. .................. ............... 56 writing, word ........... .................. .................. ............... 55 dc characteristics ........ .................. .................. ................ 167 bor ...................... .................. .................. ................ 176 brown-out reset ........ .................. ................ ............. 175 i/o pin input specifications ..... .................. ................ 174 i/o pin output specifications .. .................. ................ 175 idle current (i idle ) .................. .................. ................ 171 operating current (i dd )....................... ............. ......... 169 power-down current (i pd ) .................... .................... 173 program and eeprom................ ................ ............. 176 temperature and voltage specif ications ....... ........... 167 dead-time generators ...... .................. .................. ............. 96 ranges................ .................... ..................... ............... 96 demonstration boards picdem 1 ................ .................. .................. ............. 164 picdem 17 ................ .................. ................ ............. 165 picdem 18r ............. .................. ................ ............. 165 picdem 2 plus .......... .................. ................ ............. 164 picdem 3 ................ .................. .................. ............. 164 picdem 4 ................ .................. .................. ............. 164 picdem lin .............. .................. ................ ............. 165 picdem usb........................ .................... ................ 165 picdem.net internet/ethernet ... .................. ............. 164 development support ........ .................. ................ ............. 161 device configuration register map............ .................. .................. ............. 152 device configuration r egisters................... ............. ......... 150 fborpor ................. .................. ................ ............. 150 fgs....................... .................. .................. ................ 150 fosc ....................... .................. .................. ............. 150 fwdt................ .................... .................... ................ 150 device overview ........... ..................... .................... ............... 7 divide support............. .................... ..................... ............... 18 dsp engine................. .................... ..................... ............... 18 multiplier................ ..................... .................. ............... 20 dspic30f6010 port register map .. .................. ............ 59, 60 dual output compare match mode .. .................. ................ 82 continuous pulse mode............ .................. ................ 82 single pulse mode....... .................. ............... .............. 82 e edge aligned pwm......... .................. .................. ................ 94 electrical characteristics ........... ..................... .................. 167 ac.................. .................... ..................... .................. 177 dc ................. .................... ..................... .................. 167 equations a/d conversion clock............. .................. ................ 134 baud rate............... .................. ................ ........ 117, 127 pwm period.......... .................... .................. ................ 94 pwm resolution ..................... .................... ................ 94 serial clock rate ...... .................. ................ .............. 110 errata ....................... ....................... .................... .................. 6 evaluation and programming tools... ................. .............. 165 exception processing interrupt priority ...... .................. .................. ................ 42 exception sequence trap sources ............... .................. ............... .............. 43 external clock timing characteristics timer 1, 2, 3, 4 and 5 ........... .................... ................ 185 external clock timing requirement s ................. .............. 178 timer1 ............. ..................... .................... ................ 185 timer2 and timer4 ................. .................. ................ 186 timer3 and timer5 ................. .................. ................ 186 external interrupt requests .......... .................... .................. 45 f fast context saving ....... .................. .................. ................ 45 flash program memory .... .................. .................. .............. 47 in-circuit serial programming (i csp)........... .............. 47 run time self-programming (rt sp) ........... .............. 47 table instruction operation su mmary .......... .............. 47 i i/o pin specifications input............... .................... ..................... .................. 174 output ................... .................. .................. ................ 175 i/o ports............. ...................... ....................... .................... 57 parallel i/o (pio) ..... ................. .................. ................ 57 i 2 c 10-bit slave mode operation..... ................. ................ 107 reception ............... .................. .................. .............. 108 transmission ............ .................. ................ .............. 107 i 2 c 7-bit slave mode operation...... .................. ................ 107 reception ............... .................. .................. .............. 107 transmission ............ .................. ................ .............. 107 i 2 c master mode baud rate generator .... ...................... ..................... 110 clock arbitration ....... .................. ................ .............. 110 multi-master communication, bus collision and bus arbitration ............. ................ .............. 110 reception ............... .................. .................. .............. 110 transmission ............ .................. ................ .............. 109 i 2 c module............. .................... ..................... .................. 105 addresses............... .................. .................. .............. 107 bus data timing characteristics master mode..................... .................. .............. 198 slave mode....................... .................. .............. 200 bus data timing requirements master mode..................... .................. .............. 199 slave mode....................... .................. .............. 201 bus start/stop bits timing characteristics master mode..................... .................. .............. 198 slave mode....................... .................. .............. 200
? 2005 microchip technology inc. preliminary ds70135c-page 219 DSPIC30F4011/4012 general call address support .... .................. ............ 109 interrupts................ .................. .................. ............... 109 ipmi support ............... .................. ................ ............ 109 master operation ........ .................. ................ ............ 109 master support ...................... .................... ............... 109 operating function description .... ................ ............ 105 operation during cpu sleep and idle modes .......... 110 pin configuration ........ .................. ................ ............ 105 programmer?s model................ .................. ............... 105 register map............. .................. .................. ............ 111 registers................ .................. .................. ............... 105 slope control .............. .................. ................ ............ 109 software controlled clock str etching (stren = 1).. 108 various modes ............ .................. ................ ............ 105 idle current (i idle ) ..................... ...................... ................. 171 in-circuit serial programming (icsp) ................ ............... 139 independent pwm output .... .................. ................ ............ 97 initialization condition for rcon register case 1 ........... 148 initialization condition for rcon register case 2 ........... 148 input capture (capx) timing charac teristics ................... 188 input capture interrupts ................. .................... ................. 79 register map............. .................. .................. .............. 80 input capture module ....... .................. .................. .............. 77 in cpu sleep mode ...... .................. ................ ............ 78 simple capture event mode ....... .................. .............. 78 input capture timing requirements .................. ............... 188 input change notification module ....... .................. .............. 61 register map (bits 7-0) ............ ..................... .............. 61 input characteristics qea/qeb............. .................... .................. ............... 191 instruction addressing modes.......... ..................... .............. 35 file register instructions ......... ..................... .............. 35 fundamental modes supported....... ............... ............ 35 mac instructions......... .................. .................. ............ 36 mcu instructions ........ .................. .................. ............ 35 move and accumulator instructi ons................ ............ 36 other instructions...... .................. .................. .............. 36 instruction set overview .............. .................... ................. 156 instruction set summary... .................. .................. ............ 153 internal clock timing examples .... .................... ............... 179 internet address......... .................... .................... ............... 223 interrupt controller register map............. .................. .................. .............. 46 interrupt priority traps.................. .................... .................... ................. 43 interrupt sequence ...................... ...................... ................. 45 interrupt stack frame .............. ..................... .............. 45 interrupts .................... .................... .................... ................. 41 l load conditions ................ .................. .................. ............ 177 m memory organization........ .................. .................. .............. 23 microchip internet web site ......... .................... ................. 223 modulo addressing ........... .................. .................. .............. 36 applicability ............... .................. .................. .............. 38 operation example ....... .................. ................ ............ 37 start and end address... ................. ................ ............ 37 w address register selection .... .................. .............. 37 motor control pwm module............. ..................... .............. 91 fault timing characteristics ....... .................. ............ 190 timing characteristics ............. .................. ............... 190 timing requirements............... .................. ............... 190 mplab asm30 assembler, linker, librarian ................... 162 mplab icd 2 in-circuit debugger .... .................. ............. 163 mplab ice 2000 high-performance universal in-circuit emulator................... .................. ............... 163 mplab ice 4000 high-performance universal in-circuit emulator................... .................. ............... 163 mplab integrated development environment software .................. .................. .................. ............. 161 mplab pm3 device programmer ..... .................. ............. 163 mplink object linker/mplib obje ct librarian ................ 162 o oc/pwm module timing characteris tics ............ ............. 189 operating current (i dd ) ................... .................. ............... 169 operating frequency vs voltage dspic30fxxxx-20 (extended) ........ ............. ........... 167 oscillator operating modes (table)........... .................. ............. 140 oscillator configurations .................. .................. ............... 142 fail-safe clock monitor ............. .................. ............. 144 fast rc (frc)........... .................. ................ ............. 143 initial clock source selection ... ................. ............... 142 low power rc (lprc).............. .................. ............. 143 lp oscillator control. ................. .................. ............. 142 phase locked loop (pll) ........... ................ ............. 143 start-up timer (ost).... ............... ................ ............. 142 oscillator selection ...... .................... .................. ............... 139 oscillator start-up timer timing characteristics ............. .................. ............... 183 timing requirements ................ .................. ............. 184 output compare interrupts ............ .................... ................. 83 output compare mode register map ........... .................. .................. ............... 84 output compare module ... .................. .................. ............. 81 timing characteristics ............. .................. ............... 188 timing requirements ................ .................. ............. 188 output compare operation duri ng cpu idle mode ........... 83 output compare sleep mode operatio n ............... ............. 83 p packaging ............. ...................... ..................... ................. 209 marking.................. .................. .................. ............... 209 pickit 1 flash starter kit ............ ..................... ................. 165 picstart plus development pr ogrammer........ ............. 164 pinout descriptions........ .................. .................. ........... 10, 12 pll clock timing specifications ..... .................. ............... 179 por. see power-on reset port write/read example .............. .................... ................. 58 position measurement mode ........... .................... ............... 87 power saving modes......... .................. ................ ............. 149 idle.................. .................... ..................... ................. 150 sleep ..................... .................. .................. ............... 149 power saving modes (sleep and idle ) ................ ............. 139 power-down current (i pd )................. .................. ............. 173 power-on reset (por).................. .................... ............... 139 oscillator start-up timer (ost). .................. ............. 139 power-up timer (pwrt) ........... .................. ............. 139 power-up timer timing characteristics ............. .................. ............... 183 timing requirements ................ .................. ............. 184 pro mate ii universal device programmer ................... 163 program address space................ .................... ................. 23 construction ............ .................. .................. ............... 24 data access from program memory using table instructions .............. .................. ............... 25 data access from, address gener ation ..................... 24 memory map.............. .................. .................. ............. 23
DSPIC30F4011/4012 ds70135c-page 220 preliminary ? 2005 microchip technology inc. table instructions tblrdh................. ................ ................ ............. 25 tblrdl ................. ................ ................ ............. 25 tblwth ............................ .................. ............... 25 tblwtl................. ................ ................ ............. 25 program and eeprom characteristic s ............... ............. 176 program counter.............. .................. .................. ............... 16 program data table access ........... ..................... ............... 26 program space visibility window into program space oper ation......... ............. 27 programmable............... .................. .................. ................ 139 programmable digital noise filters. ..................... ............... 87 programmer?s model........ .................. .................. ............... 16 diagram ................... .................. .................. ............... 17 programming operations ................ ..................... ............... 49 algorithm for program flash ...... .................. ............... 49 erasing a row of program memo ry ............... ............. 49 initiating the programming sequenc e .............. ........... 50 loading write latches ............... .................. ............... 50 protection against accidental writes to osccon ........... 144 pwm duty cycle comparison units ... ................. ............... 95 duty cycle register buffers .... ..................... ............... 95 pwm fault pins ............ ..................... .................. ............... 98 enable bits............... .................. .................. ............... 98 fault states .............. .................. .................. ............... 98 modes ............... .................... .................... .................. 98 cycle-by-cycle.......... ...................... .................... 98 latched .................. ................ ................ ............. 98 pwm operation during cpu idle mo de............... ............... 99 pwm operation during cpu sleep m ode ............. ............. 99 pwm output and polarity control ... ..................... ............... 98 output pin control ..... .................. .................. ............. 98 pwm output override...... .................. .................. ............... 97 complementary output mode ...... .................. ............. 97 synchronization ........... .................. ................ ............. 97 pwm period ............ ...................... .................... .................. 94 pwm special event trigger ............ ..................... ............... 99 postscaler ................ .................. .................. ............... 99 pwm time base .............. .................. .................. ............... 93 continuous up/down counting mo des ....................... 93 double update mode ................. .................. ............... 94 free running mode ................... .................. ............... 93 postscaler ................ .................. .................. ............... 94 prescaler .................. .................. .................. ............... 94 single shot mode......... .................. ................ ............. 93 pwm update lockout ........ .................. .................. ............. 99 q qea/qeb input characteristics ...... .................. ................ 191 qei module external clock timing requireme nts........................ 187 index pulse timing characteristi cs.............. ............. 192 index pulse timing requirement s ............... ............. 192 operation during cpu idle mode .................. ............. 88 operation during cpu sleep mode ............... ............. 87 register map............ .................. .................. ............... 89 timer operation during cpu idle mode ..................... 88 timer operation during cpu sl eep mode....... ........... 87 quadrature decoder timing requ irements ......... ............. 191 quadrature encoder interface (q ei) module ....... ............... 85 quadrature encoder interface inte rrupts ............. ............... 88 quadrature encoder interface logic . ................... ............... 86 r reset ................. ...................... .................... ............. 139, 145 reset sequence ............. .................. .................. ................ 43 reset sources ............. .................. ............... .............. 43 reset timing characteristics........ .................... ................ 183 reset timing requirements ........... .................. ................ 184 resets bor, programmable ..... ...................... ..................... 147 por ...................... .................. .................. ................ 145 por with long crystal start- up time......... .............. 147 por, operating without fs cm and pwrt .............. 147 s simple capture event mode capture buffer operat ion............... ............... .............. 78 capture prescaler........ .................. ............... .............. 78 hall sensor mode ................... .................... ................ 78 input capture in cpu idle mode ................. ................ 79 timer2 and timer3 selection mo de.............. .............. 78 simple oc/pwm mode timing r equirements ................. 189 simple output compare match m ode ................ ................ 82 simple pwm mode ......... .................. .................. ................ 82 input pin fault protection ......... .................. ................ 82 period ..................... .................. .................. ................ 83 single pulse pwm operation ......... .................... ................ 97 software simulator (mplab sim) .. .................. ................ 162 software simulator (mplab sim30) .................. .............. 162 software stack pointer, frame po inter .............. ................ 16 call stack frame ...... .................. ............... .............. 31 spi mode slave select synchronization ... .................. .............. 103 spi1 register map.... .................. ................ .............. 104 spi module ................... .................. .................. ................ 101 framed spi support ...... ...................... ..................... 101 operating function description . ................. .............. 101 sdox disable ........... .................. ................ .............. 101 timing characteristics master mode (cke = 0)......... ............... ............ 193 master mode (cke = 1)......... ............... ............ 194 slave mode (cke = 1)........ ................ ...... 195, 196 timing requirements master mode (cke = 0)......... ............... ............ 193 master mode (cke = 1)......... ............... ............ 194 slave mode (cke = 0)........... ............... ............ 195 slave mode (cke = 1)........... ............... ............ 197 word and byte communication .. ................ .............. 101 spi operation during cpu idle m ode ................ .............. 103 spi operation during cpu sleep m ode............. .............. 103 status register ............. .................... .................. ................ 16 symbols used in opcode descripti ons .............. .............. 154 system integration........ .................. .................. ................ 139 overview................. .................. .................. .............. 139 register map ............ .................. ................ .............. 152 t temperature and voltage specifications ac.................. .................... ..................... .................. 177 dc ................. .................... ..................... .................. 167 timer1 module.............. .................... .................. ................ 63 16-bit asynchronous counter m ode ............. .............. 63 16-bit synchronous counter mode ............... .............. 63 16-bit timer mode........ .................. ............... .............. 63
? 2005 microchip technology inc. preliminary ds70135c-page 221 DSPIC30F4011/4012 gate operation ...................... .................... ................. 64 interrupt.............. .................... .................... ................. 65 operation during sleep mode ...... .................. ............ 64 prescaler................... .................. .................. .............. 64 real-time clock ........... .................. ................ ............ 65 rtc interrupts .................... .................. .............. 65 rtc oscillator operation...... .................. ............ 65 register map............. .................. .................. .............. 66 timer2 and timer3 selection mode . ..................... .............. 82 timer2/3 module ............ ..................... .................. .............. 67 32-bit synchronous counter mode ................. ............ 67 32-bit timer mode....... .................. .................. ............ 67 adc event trigger........ .................. ................ ............ 70 gate operation ...................... .................... ................. 70 interrupt.............. .................... .................... ................. 70 operation during sleep mode ...... .................. ............ 70 register map............. .................. .................. .............. 71 timer prescaler...................... .................... ................. 70 timer4/5 module ............ ..................... .................. .............. 73 register map............. .................. .................. .............. 76 timerq (qei module) external clock timing characteristics ....................... .................... ............... 187 timing characteristics a/d conversion 10-bit high-speed (chps = 01, simsam = 0, asam = 0, ssrc = 000) ....... .................... ................. 205 10-bit high-speed (chps = 01, simsam = 0, asam = 1, ssrc = 111, samc = 00001) .................. 206 bandgap start-up time............... .................. ............ 184 can module i/o.......... .................. ................ ............ 202 clkout and i/o......... .................. ................ ............ 182 external clock...................... .................... ................. 177 i 2 c bus data master mode ........... ....................... ................... 198 slave mode ............. ....................... ................... 200 i 2 c bus start/stop bits master mode ........... ....................... ................... 198 slave mode ............. ....................... ................... 200 input capture (capx).. .................. ................ ............ 188 motor control pwm module........ .................. ............ 190 motor control pwm module falult. ............... ............ 190 oc/pwm module .......... ................ ................ ............ 189 oscillator start-up timer .......... .................. ............... 183 output compare module............. .................. ............ 188 power-up timer .......... .................. ................ ............ 183 qei module index pulse ............. .................. ............ 192 reset...................... .................. .................. ............... 183 spi module master mode (cke = 0) ...... .................. ............ 193 master mode (cke = 1) ...... .................. ............ 194 slave mode (cke = 0) .......... ................ ............ 195 slave mode (cke = 1) .......... ................ ............ 196 timer 1, 2, 3, 4 and 5 external clock......... ............... 185 timerq (qei module) external clock ........... ............ 187 watchdog timer............ ................ ................ ............ 183 timing diagrams center aligned pwm .................. .................. .............. 95 dead-time ........... .................... ..................... .............. 96 edge aligned pwm....... .................. ................ ............ 94 pwm output ............... .................. .................. ............ 83 time-out sequence on power-up (mclr not tied to v dd ), case 1....... ............... 146 time-out sequence on power-up (mclr not tied to v dd ), case 2 ...... ............... 146 time-out sequence on power-up (mclr tied to v dd ) ..................... .................... 146 timing diagrams and specifications dc characteristics - internal rc accuracy .............. 179 timing diagrams.see timing characteristics timing requirements a/d conversion 10-bit high-speed................ ................ ............. 207 bandgap start-up time .... ....................... ................. 184 brown-out reset.................... .................... ............... 184 can module i/o ........ .................. ................ ............. 202 clkout and i/o ............ ...................... .................... 182 external clock ........... .................. ................ ............. 178 i 2 c bus data (master mode) ...... ................. ............. 199 i 2 c bus data (slave mode) ....... .................. ............. 201 input capture........... .................. .................. ............. 188 motor control pwm module ...... .................. ............. 190 oscillator start-up timer.......... .................. ............... 184 output compare module ........... .................. ............. 188 power-up timer ......... .................. ................ ............. 184 qei module external clock ........ ...................... .................... 187 index pulse...................... .................. ............... 192 quadrature decoder....... ...................... .................... 191 reset ..................... .................. .................. ............... 184 simple oc/pwm mode ............. .................. ............. 189 spi module master mode (cke = 0)....... ................ ............. 193 master mode (cke = 1)....... ................ ............. 194 slave mode (cke = 0)......... ................ ............. 195 slave mode (cke = 1)......... ................ ............. 197 timer1 external clock ........... .................... ............... 185 timer2 and timer4 external clo ck ........................... 186 timer3 and timer5 external clo ck ........................... 186 watchdog timer ...................... .................. ............... 184 timing specifications pll clock .................. .................. ................ ............. 179 trap vectors ................ .................... .................... ............... 44 u uart address detect mode .............. .................. ............... 117 auto baud support .................. .................. ............... 118 baud rate generator ................ .................. ............. 117 enabling and setting up uart ... ................ ............. 115 alternate i/o .................... .................. ............... 115 disabling................. ...................... .................... 115 enabling ................. ...................... .................... 115 setting up data, parity and stop bit selections........... ..................... ................. 115 loopback mode .............. ...................... .................... 117 module overview..................... .................. ............... 113 operation during cpu sleep and idle modes.......... 118 receiving data .......... .................. ................ ............. 116 in 8-bit or 9-bit data mode.. ................. ............. 116 interrupt ................ ............... ................ ............. 116 receive buffer (uxrcb)...... ................ ............. 116 reception error handling .......... .................. ............. 116 framing error (ferr) ......... ................ ............. 117 idle status ............ ............... ................ ............. 117 parity error (perr) .. ....................... ................. 117 receive break ........ ...................... .................... 117 receive buffer overrun e rror (oerr bit) ........ 116
DSPIC30F4011/4012 ds70135c-page 222 preliminary ? 2005 microchip technology inc. transmitting data....... .................. ................ ............. 115 in 8-bit data mode ............. .................. ............. 115 in 9-bit data mode ............. .................. ............. 115 interrupt................ ................ ................ ............. 116 transmit buffer (uxtxb)........ ................ ........... 115 uart1 register map .............. .................. ................ 119 uart2 register map .............. .................. ................ 119 unit id locations......... .................... .................. ................ 139 universal asynchronous receiver transmitter module (uart) ............ ................ ................ ............. 113 w wake-up from sleep ..... .................. .................. ................ 139 wake-up from sleep and idle ......... .................... ................ 45 watchdog timer timing characteristics ............ .................. ................ 183 timing requirements..... ...................... ..................... 184 watchdog timer (wdt)................ .................. .......... 139, 149 enabling and disabling ............. .................. .............. 149 operation ................ .................. .................. .............. 149 www address ............. .................. .................. ................ 223 www, on-line support ...... .................. .................. ............. 6
? 2005 microchip technology inc. preliminary ds70135c-page 223 DSPIC30F4011/4012 the microchip web site microchip provides online su pport via our www site at www.microchip.com. this web si te is used as a means to make files and inform ation easily available to customers. accessible by us ing your favorite internet browser, the web site contains the following information: product support ? data sheets and errata, application notes and sample programs, design resources, user?s guid es and hardware support documents, latest software releases and archived software general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notif ication service helps keep customers current on microc hip products. subscribers will receive e-mail notifica tion whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow t he registration instructions. customer support users of microchip produc ts can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com in addition, there is a de velopment systems informa- tion line which lists the latest versions of microchip?s development systems software products. this line also provides information on how customers can receive currently available upgrade kits. the development systems information line numbers are: 1-800-755-2345 ? united stat es and most of canada 1-480-792-7302 ? other in ternational locations
DSPIC30F4011/4012 ds70135c-page 224 preliminary ? 2005 microchip technology inc. reader response it is our intention to provide yo u with the best documentation possible to en sure successful use of your microchip prod- uct. if you wish to provide your comm ents on organization, clarity, subject matt er, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us wi th your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _ ________ - _________ ds70135c DSPIC30F4011/4012 1. what are the best features of this document? 2. how does this document meet your ha rdware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or mislead ing information (what and where)? 7. how would you improve this document?
? 2005 microchip technology inc. preliminary ds70135c-page 225 DSPIC30F4011/4012 product identification system to order or obtain information, e.g ., on pricing or delivery, refer to the factory or the list ed sales office. dspic30f6010at-30i/pf-000 example: dspic30f6010at-30i/pf = 30 mips, indu strial temp., tqfp package, rev. a trademark architecture flash e = extended high temp -40c to +125c i = industrial -40c to +85c temperature device id package pf = tqfp 14x14 s = die (waffle pack) w = die (wafers) memory size in bytes 0 = romless 1 = 1k to 6k 2 = 7k to 12k 3 = 13k to 24k 4 = 25k to 48k 5 = 49k to 96k 6 = 97k to 192k 7 = 193k to 384k 8 = 385k to 768k 9 = 769k and up custom id (3 digits) or t = tape and reel a,b,c? = revision level engineering sample (es) speed 20 = 20 mips 30 = 30 mips
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